[PATCH v1 1/1] iio: adc: nxp-sar-adc: Avoid division by zero

[PATCH v1 1/1] iio: adc: nxp-sar-adc: Avoid division by zero

[Andy Shevchenko]

When Common Clock Framework is disabled, clk_get_rate() returns 0.
This is used as part of the divisor to perform nanosecond delays
with help of ndelay(). When the above condition occurs the compiler,
due to unspecified behaviour, is free to do what it wants to. Here
it saturates the value, which is logical from mathematics point of
view. However, the ndelay() implementation has set a reasonable
upper threshold and refuses to provide anything for such a long
delay. That's why code may not be linked under these circumstances.

To solve the issue, provide a wrapper that calls ndelay() when
the value is known not to be zero.

Fixes: 4434072a893e ("iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202603311958.ly6uROit-lkp@intel.com/
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/iio/adc/nxp-sar-adc.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/nxp-sar-adc.c b/drivers/iio/adc/nxp-sar-adc.c
index 9d9f2c76bed4..705dd7da1bd2 100644
--- a/drivers/iio/adc/nxp-sar-adc.c
+++ b/drivers/iio/adc/nxp-sar-adc.c
@@ -198,6 +198,15 @@ static void nxp_sar_adc_irq_cfg(struct nxp_sar_adc *info, bool enable)
 		writel(0, NXP_SAR_ADC_IMR(info->regs));
 }
 
+static void nxp_sar_adc_wait_for(struct nxp_sar_adc *info, unsigned int cycles)
+{
+	u64 rate;
+
+	rate = clk_get_rate(info->clk);
+	if (rate)
+		ndelay(div64_u64(NSEC_PER_SEC, rate * cycles));
+}
+
 static bool nxp_sar_adc_set_enabled(struct nxp_sar_adc *info, bool enable)
 {
 	u32 mcr;
@@ -221,7 +230,7 @@ static bool nxp_sar_adc_set_enabled(struct nxp_sar_adc *info, bool enable)
 	 * configuration of NCMR and the setting of NSTART.
 	 */
 	if (enable)
-		ndelay(div64_u64(NSEC_PER_SEC, clk_get_rate(info->clk) * 3));
+		nxp_sar_adc_wait_for(info, 3);
 
 	return pwdn;
 }
@@ -469,7 +478,7 @@ static void nxp_sar_adc_stop_conversion(struct nxp_sar_adc *info)
 	 * only when the capture finishes. The delay will be very
 	 * short, usec-ish, which is acceptable in the atomic context.
 	 */
-	ndelay(div64_u64(NSEC_PER_SEC, clk_get_rate(info->clk)) * 80);
+	nxp_sar_adc_wait_for(info, 80);
 }
 
 static int nxp_sar_adc_start_conversion(struct nxp_sar_adc *info, bool raw)
-- 
2.50.1

Re: [PATCH v1 1/1] iio: adc: nxp-sar-adc: Avoid division by zero

[Daniel Lezcano]

Hi Andy,

On 4/16/26 11:01, Andy Shevchenko wrote:
> When Common Clock Framework is disabled, clk_get_rate() returns 0.
> This is used as part of the divisor to perform nanosecond delays
> with help of ndelay(). When the above condition occurs the compiler,
> due to unspecified behaviour, is free to do what it wants to. Here
> it saturates the value, which is logical from mathematics point of
> view. However, the ndelay() implementation has set a reasonable
> upper threshold and refuses to provide anything for such a long
> delay. That's why code may not be linked under these circumstances.
> 
> To solve the issue, provide a wrapper that calls ndelay() when
> the value is known not to be zero.
> 
> Fixes: 4434072a893e ("iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms")
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202603311958.ly6uROit-lkp@intel.com/
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Acked-by: Daniel Lezcano <daniel.lezcano@oss.qualcomm.com>

> ---
>   drivers/iio/adc/nxp-sar-adc.c | 13 +++++++++++--
>   1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/iio/adc/nxp-sar-adc.c b/drivers/iio/adc/nxp-sar-adc.c
> index 9d9f2c76bed4..705dd7da1bd2 100644
> --- a/drivers/iio/adc/nxp-sar-adc.c
> +++ b/drivers/iio/adc/nxp-sar-adc.c
> @@ -198,6 +198,15 @@ static void nxp_sar_adc_irq_cfg(struct nxp_sar_adc *info, bool enable)
>   		writel(0, NXP_SAR_ADC_IMR(info->regs));
>   }
>   
> +static void nxp_sar_adc_wait_for(struct nxp_sar_adc *info, unsigned int cycles)
> +{
> +	u64 rate;
> +
> +	rate = clk_get_rate(info->clk);
> +	if (rate)
> +		ndelay(div64_u64(NSEC_PER_SEC, rate * cycles));
> +}
> +
>   static bool nxp_sar_adc_set_enabled(struct nxp_sar_adc *info, bool enable)
>   {
>   	u32 mcr;
> @@ -221,7 +230,7 @@ static bool nxp_sar_adc_set_enabled(struct nxp_sar_adc *info, bool enable)
>   	 * configuration of NCMR and the setting of NSTART.
>   	 */
>   	if (enable)
> -		ndelay(div64_u64(NSEC_PER_SEC, clk_get_rate(info->clk) * 3));
> +		nxp_sar_adc_wait_for(info, 3);
>   
>   	return pwdn;
>   }
> @@ -469,7 +478,7 @@ static void nxp_sar_adc_stop_conversion(struct nxp_sar_adc *info)
>   	 * only when the capture finishes. The delay will be very
>   	 * short, usec-ish, which is acceptable in the atomic context.
>   	 */
> -	ndelay(div64_u64(NSEC_PER_SEC, clk_get_rate(info->clk)) * 80);
> +	nxp_sar_adc_wait_for(info, 80);
>   }
>   
>   static int nxp_sar_adc_start_conversion(struct nxp_sar_adc *info, bool raw)