* [PATCH v5 1/6] dt-bindings: pwm: Add a new binding for rockchip,rk3576-pwm
2026-04-20 13:52 [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Nicolas Frattaroli
@ 2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 2/6] mfd: Add Rockchip mfpwm driver Nicolas Frattaroli
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Nicolas Frattaroli @ 2026-04-20 13:52 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Lee Jones, William Breathitt Gray,
Damon Ding
Cc: Nicolas Frattaroli, kernel, Jonas Karlman, Alexey Charkov,
linux-rockchip, linux-pwm, devicetree, linux-arm-kernel,
linux-kernel, linux-iio, Conor Dooley
The Rockchip RK3576 SoC has a newer PWM controller IP revision than
previous Rockchip SoCs. This IP, called "PWMv4" by Rockchip, introduces
several new features, and consequently differs in its bindings.
Instead of expanding the ever-growing rockchip-pwm binding that already
has an if-condition, add an entirely new binding to handle this.
There are two additional clocks, "osc" and "rc". These are available for
every PWM instance, and the PWM hardware can switch between the "pwm",
"osc" and "rc" clock at runtime.
The PWM controller also comes with an interrupt now. This interrupt is
used to signal various conditions.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
.../bindings/pwm/rockchip,rk3576-pwm.yaml | 77 ++++++++++++++++++++++
MAINTAINERS | 7 ++
2 files changed, 84 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/rockchip,rk3576-pwm.yaml b/Documentation/devicetree/bindings/pwm/rockchip,rk3576-pwm.yaml
new file mode 100644
index 000000000000..48d5055c8b06
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/rockchip,rk3576-pwm.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/rockchip,rk3576-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip PWMv4 controller
+
+maintainers:
+ - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+
+description: |
+ The Rockchip PWMv4 controller is a PWM controller found on several Rockchip
+ SoCs, such as the RK3576.
+
+ It supports both generating and capturing PWM signals.
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: rockchip,rk3576-pwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Used to derive the PWM signal.
+ - description: Used as the APB bus clock.
+ - description: Used as an alternative to derive the PWM signal.
+ - description: Used as another alternative to derive the PWM signal.
+
+ clock-names:
+ items:
+ - const: pwm
+ - const: pclk
+ - const: osc
+ - const: rc
+
+ interrupts:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3576-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pwm@2add0000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2add0000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>,
+ <&cru CLK_RC_PWM1>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 891fb83ba7a9..86f20cb563c6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23172,6 +23172,13 @@ F: Documentation/userspace-api/media/v4l/metafmt-rkisp1.rst
F: drivers/media/platform/rockchip/rkisp1
F: include/uapi/linux/rkisp1-config.h
+ROCKCHIP MFPWM
+M: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+L: linux-rockchip@lists.infradead.org
+L: linux-pwm@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/pwm/rockchip,rk3576-pwm.yaml
+
ROCKCHIP RK3568 RANDOM NUMBER GENERATOR SUPPORT
M: Daniel Golle <daniel@makrotopia.org>
M: Aurelien Jarno <aurelien@aurel32.net>
--
2.53.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 2/6] mfd: Add Rockchip mfpwm driver
2026-04-20 13:52 [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 1/6] dt-bindings: pwm: Add a new binding for rockchip,rk3576-pwm Nicolas Frattaroli
@ 2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 3/6] pwm: Add rockchip PWMv4 driver Nicolas Frattaroli
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Nicolas Frattaroli @ 2026-04-20 13:52 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Lee Jones, William Breathitt Gray,
Damon Ding
Cc: Nicolas Frattaroli, kernel, Jonas Karlman, Alexey Charkov,
linux-rockchip, linux-pwm, devicetree, linux-arm-kernel,
linux-kernel, linux-iio
With the Rockchip RK3576, the PWM IP used by Rockchip has changed
substantially. Looking at both the downstream pwm-rockchip driver as
well as the mainline pwm-rockchip driver made it clear that with all its
additional features and its differences from previous IP revisions, it
is best supported in a new driver.
This brings us to the question as to what such a new driver should be.
To me, it soon became clear that it should actually be several new
drivers, most prominently when Uwe Kleine-König let me know that I
should not implement the pwm subsystem's capture callback, but instead
write a counter driver for this functionality.
Combined with the other as-of-yet unimplemented functionality of this
new IP, it became apparent that it needs to be spread across several
subsystems.
For this reason, we add a new MFD core driver, called mfpwm (short for
"Multi-function PWM"). This "parent" driver makes sure that only one
device function driver is using the device at a time, and is in charge
of registering the MFD cell devices for the individual device functions
offered by the device.
An acquire/release pattern is used to guarantee that device function
drivers don't step on each other's toes.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
MAINTAINERS | 2 +
drivers/mfd/Kconfig | 16 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/rockchip-mfpwm.c | 357 ++++++++++++++++++++++++++++
include/linux/mfd/rockchip-mfpwm.h | 470 +++++++++++++++++++++++++++++++++++++
5 files changed, 846 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 86f20cb563c6..d52731242a33 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23178,6 +23178,8 @@ L: linux-rockchip@lists.infradead.org
L: linux-pwm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pwm/rockchip,rk3576-pwm.yaml
+F: drivers/mfd/rockchip-mfpwm.c
+F: include/linux/mfd/rockchip-mfpwm.h
ROCKCHIP RK3568 RANDOM NUMBER GENERATOR SUPPORT
M: Daniel Golle <daniel@makrotopia.org>
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 7192c9d1d268..80b4e82c4937 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1378,6 +1378,22 @@ config MFD_RC5T583
Additional drivers must be enabled in order to use the
different functionality of the device.
+config MFD_ROCKCHIP_MFPWM
+ tristate "Rockchip multi-function PWM controller"
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ depends on OF
+ depends on HAS_IOMEM
+ depends on COMMON_CLK
+ select MFD_CORE
+ help
+ Some Rockchip SoCs, such as the RK3576, use a PWM controller that has
+ several different functions, such as generating PWM waveforms but also
+ counting waveforms.
+
+ This driver manages the overall device, and selects between different
+ functionalities at runtime as needed. Drivers for them are implemented
+ in their respective subsystems.
+
config MFD_RK8XX
tristate
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index e75e8045c28a..ebadbaea9e4a 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -231,6 +231,7 @@ obj-$(CONFIG_MFD_PALMAS) += palmas.o
obj-$(CONFIG_MFD_VIPERBOARD) += viperboard.o
obj-$(CONFIG_MFD_NTXEC) += ntxec.o
obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o
+obj-$(CONFIG_MFD_ROCKCHIP_MFPWM) += rockchip-mfpwm.o
obj-$(CONFIG_MFD_RK8XX) += rk8xx-core.o
obj-$(CONFIG_MFD_RK8XX_I2C) += rk8xx-i2c.o
obj-$(CONFIG_MFD_RK8XX_SPI) += rk8xx-spi.o
diff --git a/drivers/mfd/rockchip-mfpwm.c b/drivers/mfd/rockchip-mfpwm.c
new file mode 100644
index 000000000000..72d04982b961
--- /dev/null
+++ b/drivers/mfd/rockchip-mfpwm.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ *
+ * A driver to manage all the different functionalities exposed by Rockchip's
+ * PWMv4 hardware.
+ *
+ * This driver is chiefly focused on guaranteeing non-concurrent operation
+ * between the different device functions, as well as setting the clocks.
+ * It registers the device function platform devices, e.g. PWM output or
+ * PWM capture.
+ *
+ * Authors:
+ * Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+ */
+
+#include <linux/array_size.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/rockchip-mfpwm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/overflow.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+/**
+ * struct rockchip_mfpwm - private mfpwm driver instance state struct
+ * @pdev: pointer to this instance's &struct platform_device
+ * @base: pointer to the memory mapped registers of this device
+ * @pwm_clk: pointer to the PLL clock the PWM signal may be derived from
+ * @osc_clk: pointer to the fixed crystal the PWM signal may be derived from
+ * @rc_clk: pointer to the RC oscillator the PWM signal may be derived from
+ * @chosen_clk: a clk-mux of pwm_clk, osc_clk and rc_clk
+ * @pclk: pointer to the APB bus clock needed for mmio register access
+ * @active_func: pointer to the currently active device function, or %NULL if no
+ * device function is currently actively using any of the shared
+ * resources. May only be checked/modified with @state_lock held.
+ * @acquire_cnt: number of times @active_func has currently mfpwm_acquire()'d
+ * it. Must only be checked or modified while holding @state_lock.
+ * @state_lock: this lock is held while either the active device function, the
+ * enable register, or the chosen clock is being changed.
+ * @irq: the IRQ number of this device
+ */
+struct rockchip_mfpwm {
+ struct platform_device *pdev;
+ void __iomem *base;
+ struct clk *pwm_clk;
+ struct clk *osc_clk;
+ struct clk *rc_clk;
+ struct clk *chosen_clk;
+ struct clk *pclk;
+ struct rockchip_mfpwm_func *active_func;
+ unsigned int acquire_cnt;
+ spinlock_t state_lock;
+ int irq;
+};
+
+static atomic_t subdev_id = ATOMIC_INIT(0);
+
+static inline struct rockchip_mfpwm *to_rockchip_mfpwm(struct platform_device *pdev)
+{
+ return platform_get_drvdata(pdev);
+}
+
+static int mfpwm_check_pwmf(const struct rockchip_mfpwm_func *pwmf,
+ const char *fname)
+{
+ struct device *dev = &pwmf->parent->pdev->dev;
+
+ if (IS_ERR_OR_NULL(pwmf)) {
+ dev_warn(dev, "called %s with an erroneous handle, no effect\n",
+ fname);
+ return -EINVAL;
+ }
+
+ if (IS_ERR_OR_NULL(pwmf->parent)) {
+ dev_warn(dev, "called %s with an erroneous mfpwm_func parent, no effect\n",
+ fname);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+__attribute__((nonnull))
+static int mfpwm_do_acquire(struct rockchip_mfpwm_func *pwmf)
+{
+ struct rockchip_mfpwm *mfpwm = pwmf->parent;
+ unsigned int cnt;
+
+ if (mfpwm->active_func && pwmf->id != mfpwm->active_func->id)
+ return -EBUSY;
+
+ if (!mfpwm->active_func)
+ mfpwm->active_func = pwmf;
+
+ if (!check_add_overflow(mfpwm->acquire_cnt, 1, &cnt)) {
+ mfpwm->acquire_cnt = cnt;
+ } else {
+ dev_warn(&mfpwm->pdev->dev, "prevented acquire counter overflow in %s\n",
+ __func__);
+ return -EOVERFLOW;
+ }
+
+ dev_dbg(&mfpwm->pdev->dev, "%d acquired mfpwm, acquires now at %u\n",
+ pwmf->id, mfpwm->acquire_cnt);
+
+ return clk_enable(mfpwm->pclk);
+}
+
+int mfpwm_acquire(struct rockchip_mfpwm_func *pwmf)
+{
+ struct rockchip_mfpwm *mfpwm;
+ unsigned long flags;
+ int ret = 0;
+
+ ret = mfpwm_check_pwmf(pwmf, "mfpwm_acquire");
+ if (ret)
+ return ret;
+
+ mfpwm = pwmf->parent;
+ dev_dbg(&mfpwm->pdev->dev, "%d is attempting to acquire\n", pwmf->id);
+
+ if (!spin_trylock_irqsave(&mfpwm->state_lock, flags))
+ return -EBUSY;
+
+ ret = mfpwm_do_acquire(pwmf);
+
+ spin_unlock_irqrestore(&mfpwm->state_lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_NS_GPL(mfpwm_acquire, "ROCKCHIP_MFPWM");
+
+__attribute__((nonnull))
+static void mfpwm_do_release(const struct rockchip_mfpwm_func *pwmf)
+{
+ struct rockchip_mfpwm *mfpwm = pwmf->parent;
+
+ if (!mfpwm->active_func)
+ return;
+
+ if (mfpwm->active_func->id != pwmf->id)
+ return;
+
+ /*
+ * No need to check_sub_overflow here, !mfpwm->active_func above catches
+ * this type of problem already.
+ */
+ mfpwm->acquire_cnt--;
+
+ if (!mfpwm->acquire_cnt)
+ mfpwm->active_func = NULL;
+
+ clk_disable(mfpwm->pclk);
+}
+
+void mfpwm_release(const struct rockchip_mfpwm_func *pwmf)
+{
+ struct rockchip_mfpwm *mfpwm;
+ unsigned long flags;
+
+ if (mfpwm_check_pwmf(pwmf, "mfpwm_release"))
+ return;
+
+ mfpwm = pwmf->parent;
+
+ spin_lock_irqsave(&mfpwm->state_lock, flags);
+ mfpwm_do_release(pwmf);
+ dev_dbg(&mfpwm->pdev->dev, "%d released mfpwm, acquires now at %u\n",
+ pwmf->id, mfpwm->acquire_cnt);
+ spin_unlock_irqrestore(&mfpwm->state_lock, flags);
+}
+EXPORT_SYMBOL_NS_GPL(mfpwm_release, "ROCKCHIP_MFPWM");
+
+int mfpwm_get_mode(const struct rockchip_mfpwm_func *pwmf)
+{
+ struct rockchip_mfpwm *mfpwm;
+ int ret;
+
+ ret = mfpwm_check_pwmf(pwmf, "mfpwm_acquire");
+ if (ret)
+ return ret;
+
+ mfpwm = pwmf->parent;
+
+ guard(spinlock_irqsave)(&mfpwm->state_lock);
+
+ if (!rockchip_pwm_v4_is_enabled(mfpwm_reg_read(mfpwm->base, PWMV4_REG_ENABLE)))
+ return -1;
+
+ return mfpwm_reg_read(mfpwm->base, PWMV4_REG_CTRL) & PWMV4_MODE_MASK;
+}
+EXPORT_SYMBOL_NS_GPL(mfpwm_get_mode, "ROCKCHIP_MFPWM");
+
+/**
+ * mfpwm_register_subdev - register a single mfpwm_func
+ * @mfpwm: pointer to the parent &struct rockchip_mfpwm
+ * @name: sub-device name string
+ *
+ * Allocate a single &struct mfpwm_func, fill its members with appropriate data,
+ * and register a new mfd cell.
+ *
+ * Returns: 0 on success, negative errno on error
+ */
+static int mfpwm_register_subdev(struct rockchip_mfpwm *mfpwm,
+ const char *name)
+{
+ struct rockchip_mfpwm_func *func;
+ struct mfd_cell cell = {};
+
+ func = devm_kzalloc(&mfpwm->pdev->dev, sizeof(*func), GFP_KERNEL);
+ if (IS_ERR(func))
+ return PTR_ERR(func);
+ func->irq = mfpwm->irq;
+ func->parent = mfpwm;
+ func->id = atomic_inc_return(&subdev_id);
+ func->base = mfpwm->base;
+ func->core = mfpwm->chosen_clk;
+ cell.name = name;
+ cell.platform_data = func;
+ cell.pdata_size = sizeof(*func);
+
+ return devm_mfd_add_devices(&mfpwm->pdev->dev, func->id, &cell, 1, NULL,
+ 0, NULL);
+}
+
+static int mfpwm_register_subdevs(struct rockchip_mfpwm *mfpwm)
+{
+ int ret;
+
+ ret = mfpwm_register_subdev(mfpwm, "rockchip-pwm-v4");
+ if (ret)
+ return ret;
+
+ ret = mfpwm_register_subdev(mfpwm, "rockchip-pwm-capture");
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_mfpwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rockchip_mfpwm *mfpwm;
+ char *clk_mux_name;
+ const char *mux_p_names[3];
+ int ret = 0;
+
+ mfpwm = devm_kzalloc(&pdev->dev, sizeof(*mfpwm), GFP_KERNEL);
+ if (IS_ERR(mfpwm))
+ return PTR_ERR(mfpwm);
+
+ mfpwm->pdev = pdev;
+
+ spin_lock_init(&mfpwm->state_lock);
+
+ mfpwm->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(mfpwm->base))
+ return dev_err_probe(dev, PTR_ERR(mfpwm->base),
+ "failed to ioremap address\n");
+
+ mfpwm->pclk = devm_clk_get_prepared(dev, "pclk");
+ if (IS_ERR(mfpwm->pclk))
+ return dev_err_probe(dev, PTR_ERR(mfpwm->pclk),
+ "couldn't get and prepare 'pclk' clock\n");
+
+ mfpwm->irq = platform_get_irq(pdev, 0);
+ if (mfpwm->irq < 0)
+ return dev_err_probe(dev, mfpwm->irq, "couldn't get irq 0\n");
+
+ mfpwm->pwm_clk = devm_clk_get_prepared(dev, "pwm");
+ if (IS_ERR(mfpwm->pwm_clk))
+ return dev_err_probe(dev, PTR_ERR(mfpwm->pwm_clk),
+ "couldn't get and prepare 'pwm' clock\n");
+
+ mfpwm->osc_clk = devm_clk_get_prepared(dev, "osc");
+ if (IS_ERR(mfpwm->osc_clk))
+ return dev_err_probe(dev, PTR_ERR(mfpwm->osc_clk),
+ "couldn't get and prepare 'osc' clock\n");
+
+ mfpwm->rc_clk = devm_clk_get_prepared(dev, "rc");
+ if (IS_ERR(mfpwm->rc_clk))
+ return dev_err_probe(dev, PTR_ERR(mfpwm->rc_clk),
+ "couldn't get and prepare 'rc' clock\n");
+
+ clk_mux_name = devm_kasprintf(dev, GFP_KERNEL, "%s_chosen", dev_name(dev));
+ if (!clk_mux_name)
+ return -ENOMEM;
+
+ mux_p_names[0] = __clk_get_name(mfpwm->pwm_clk);
+ mux_p_names[1] = __clk_get_name(mfpwm->osc_clk);
+ mux_p_names[2] = __clk_get_name(mfpwm->rc_clk);
+ mfpwm->chosen_clk = clk_register_mux(dev, clk_mux_name, mux_p_names,
+ ARRAY_SIZE(mux_p_names),
+ CLK_SET_RATE_PARENT,
+ mfpwm->base + PWMV4_REG_CLK_CTRL,
+ PWMV4_CLK_SRC_SHIFT, PWMV4_CLK_SRC_WIDTH,
+ CLK_MUX_HIWORD_MASK, NULL);
+ ret = clk_prepare(mfpwm->chosen_clk);
+ if (ret) {
+ dev_err(dev, "failed to prepare PWM clock mux: %pe\n",
+ ERR_PTR(ret));
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, mfpwm);
+
+ ret = mfpwm_register_subdevs(mfpwm);
+ if (ret) {
+ dev_err(dev, "failed to register sub-devices: %pe\n",
+ ERR_PTR(ret));
+ return ret;
+ }
+
+ return ret;
+}
+
+static void rockchip_mfpwm_remove(struct platform_device *pdev)
+{
+ struct rockchip_mfpwm *mfpwm = to_rockchip_mfpwm(pdev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&mfpwm->state_lock, flags);
+
+ if (mfpwm->chosen_clk) {
+ clk_unprepare(mfpwm->chosen_clk);
+ clk_unregister_mux(mfpwm->chosen_clk);
+ }
+
+ spin_unlock_irqrestore(&mfpwm->state_lock, flags);
+}
+
+static const struct of_device_id rockchip_mfpwm_of_match[] = {
+ {
+ .compatible = "rockchip,rk3576-pwm",
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rockchip_mfpwm_of_match);
+
+static struct platform_driver rockchip_mfpwm_driver = {
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = rockchip_mfpwm_of_match,
+ },
+ .probe = rockchip_mfpwm_probe,
+ .remove = rockchip_mfpwm_remove,
+};
+module_platform_driver(rockchip_mfpwm_driver);
+
+MODULE_AUTHOR("Nicolas Frattaroli <nicolas.frattaroli@collabora.com>");
+MODULE_DESCRIPTION("Rockchip MFPWM Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/rockchip-mfpwm.h b/include/linux/mfd/rockchip-mfpwm.h
new file mode 100644
index 000000000000..dbf1588a4382
--- /dev/null
+++ b/include/linux/mfd/rockchip-mfpwm.h
@@ -0,0 +1,470 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ *
+ * Common header file for all the Rockchip Multi-function PWM controller
+ * drivers that are spread across subsystems.
+ *
+ * Authors:
+ * Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+ */
+
+#ifndef __SOC_ROCKCHIP_MFPWM_H__
+#define __SOC_ROCKCHIP_MFPWM_H__
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/hw_bitfield.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+
+struct rockchip_mfpwm;
+
+/**
+ * struct rockchip_mfpwm_func - struct representing a single function driver
+ *
+ * @id: unique id for this function driver instance
+ * @base: pointer to start of MMIO registers
+ * @parent: a pointer to the parent mfpwm struct
+ * @irq: the shared IRQ gotten from the parent mfpwm device
+ * @core: a pointer to the clk mux that drives this channel's PWM
+ */
+struct rockchip_mfpwm_func {
+ int id;
+ void __iomem *base;
+ struct rockchip_mfpwm *parent;
+ int irq;
+ struct clk *core;
+};
+
+/*
+ * PWMV4 Register Definitions
+ * --------------------------
+ *
+ * Attributes:
+ * RW - Read-Write
+ * RO - Read-Only
+ * WO - Write-Only
+ * W1T - Write high, Self-clearing
+ * W1C - Write high to clear interrupt
+ *
+ * Bit ranges to be understood with Verilog-like semantics,
+ * e.g. [03:00] is 4 bits: 0, 1, 2 and 3.
+ *
+ * All registers must be accessed with 32-bit width accesses only
+ */
+
+#define PWMV4_REG_VERSION 0x000
+/*
+ * VERSION Register Description
+ * [31:24] RO | Hardware Major Version
+ * [23:16] RO | Hardware Minor Version
+ * [15:15] RO | Reserved
+ * [14:14] RO | Hardware supports biphasic counters
+ * [13:13] RO | Hardware supports filters
+ * [12:12] RO | Hardware supports waveform generation
+ * [11:11] RO | Hardware supports counter
+ * [10:10] RO | Hardware supports frequency metering
+ * [09:09] RO | Hardware supports power key functionality
+ * [08:08] RO | Hardware supports infrared transmissions
+ * [07:04] RO | Channel index of this instance
+ * [03:00] RO | Number of channels the base instance supports
+ */
+
+#define PWMV4_REG_ENABLE 0x004
+/*
+ * ENABLE Register Description
+ * [31:16] WO | Write Enable Mask for the lower half of the register
+ * Set bit `n` here to 1 if you wish to modify bit `n >> 16` in
+ * the same write operation
+ * [15:06] RO | Reserved
+ * [05:05] RW | PWM Channel Counter Read Enable, 1 = enabled
+ */
+#define PWMV4_CHN_CNT_RD_EN(v) FIELD_PREP_WM16(BIT(5), (v))
+/*
+ * [04:04] W1T | PWM Globally Joined Control Enable
+ * 1 = this PWM channel will be enabled by a global pwm enable
+ * bit instead of the PWM Enable bit.
+ */
+#define PWMV4_GLOBAL_CTRL_EN(v) FIELD_PREP_WM16(BIT(4), (v))
+/*
+ * [03:03] RW | Force Clock Enable
+ * 0 = disabled, if the PWM channel is inactive then so is the
+ * clock prescale module
+ */
+#define PWMV4_FORCE_CLK_EN(v) FIELD_PREP_WM16(BIT(3), (v))
+/*
+ * [02:02] W1T | PWM Control Update Enable
+ * 1 = enabled, commits modifications of _CTRL, _PERIOD, _DUTY and
+ * _OFFSET registers once 1 is written to it
+ */
+#define PWMV4_CTRL_UPDATE_EN FIELD_PREP_WM16_CONST(BIT(2), 1)
+/*
+ * [01:01] RW | PWM Enable, 1 = enabled
+ * If in one-shot mode, clears after end of operation
+ */
+#define PWMV4_EN_MASK BIT(1)
+#define PWMV4_EN(v) FIELD_PREP_WM16(PWMV4_EN_MASK, \
+ ((v) ? 1 : 0))
+/*
+ * [00:00] RW | PWM Clock Enable, 1 = enabled
+ * If in one-shot mode, clears after end of operation
+ */
+#define PWMV4_CLK_EN_MASK BIT(0)
+#define PWMV4_CLK_EN(v) FIELD_PREP_WM16(PWMV4_CLK_EN_MASK, \
+ ((v) ? 1 : 0))
+#define PWMV4_EN_BOTH_MASK (PWMV4_EN_MASK | PWMV4_CLK_EN_MASK)
+static inline __pure bool rockchip_pwm_v4_is_enabled(unsigned int val)
+{
+ return (val & PWMV4_EN_BOTH_MASK);
+}
+
+#define PWMV4_REG_CLK_CTRL 0x008
+/*
+ * CLK_CTRL Register Description
+ * [31:16] WO | Write Enable Mask for the lower half of the register
+ * Set bit `n` here to 1 if you wish to modify bit `n >> 16` in
+ * the same write operation
+ * [15:15] RW | Clock Global Selection
+ * 0 = current channel scale clock
+ * 1 = global channel scale clock
+ */
+#define PWMV4_CLK_GLOBAL(v) FIELD_PREP_WM16(BIT(15), (v))
+/*
+ * [14:13] RW | Clock Source Selection
+ * 0 = Clock from PLL, frequency can be configured
+ * 1 = Clock from crystal oscillator, frequency is fixed
+ * 2 = Clock from RC oscillator, frequency is fixed
+ * 3 = Reserved
+ * NOTE: The purpose for this clock-mux-outside-CRU construct is
+ * to let the SoC go into a sleep state with the PWM
+ * hardware still having a clock signal for IR input, which
+ * can then wake up the SoC.
+ */
+#define PWMV4_CLK_SRC_PLL 0x0U
+#define PWMV4_CLK_SRC_CRYSTAL 0x1U
+#define PWMV4_CLK_SRC_RC 0x2U
+#define PWMV4_CLK_SRC_SHIFT 13
+#define PWMV4_CLK_SRC_WIDTH 2
+/*
+ * [12:04] RW | Scale Factor to apply to pre-scaled clock
+ * 1 <= v <= 256, v means clock divided by 2*v
+ */
+#define PWMV4_CLK_SCALE_F(v) FIELD_PREP_WM16(GENMASK(12, 4), (v))
+/*
+ * [03:03] RO | Reserved
+ * [02:00] RW | Prescale Factor
+ * v here means the input clock is divided by pow(2, v)
+ */
+#define PWMV4_CLK_PRESCALE_F(v) FIELD_PREP_WM16(GENMASK(2, 0), (v))
+
+#define PWMV4_REG_CTRL 0x00C
+/*
+ * CTRL Register Description
+ * [31:16] WO | Write Enable Mask for the lower half of the register
+ * Set bit `n` here to 1 if you wish to modify bit `n >> 16` in
+ * the same write operation
+ * [15:09] RO | Reserved
+ * [08:06] RW | PWM Input Channel Selection
+ * By default, the channel selects its own input, but writing v
+ * here selects PWM input from channel v instead.
+ */
+#define PWMV4_CTRL_IN_SEL(v) FIELD_PREP_WM16(GENMASK(8, 6), (v))
+/* [05:05] RW | Aligned Mode, 0 = Valid, 1 = Invalid */
+#define PWMV4_CTRL_UNALIGNED(v) FIELD_PREP_WM16(BIT(5), (v))
+/* [04:04] RW | Output Mode, 0 = Left Aligned, 1 = Centre Aligned */
+#define PWMV4_LEFT_ALIGNED 0x0U
+#define PWMV4_CENTRE_ALIGNED 0x1U
+#define PWMV4_CTRL_OUT_MODE(v) FIELD_PREP_WM16(BIT(4), (v))
+/*
+ * [03:03] RW | Inactive Polarity for when the channel is either disabled or
+ * has completed outputting the entire waveform in one-shot mode.
+ * 0 = Negative, 1 = Positive
+ */
+#define PWMV4_POLARITY_N 0x0U
+#define PWMV4_POLARITY_P 0x1U
+#define PWMV4_INACTIVE_POL(v) FIELD_PREP_WM16(BIT(3), (v))
+/*
+ * [02:02] RW | Duty Cycle Polarity to use at the start of the waveform.
+ * 0 = Negative, 1 = Positive
+ */
+#define PWMV4_DUTY_POL_SHIFT 2
+#define PWMV4_DUTY_POL_MASK BIT(PWMV4_DUTY_POL_SHIFT)
+#define PWMV4_DUTY_POL(v) FIELD_PREP_WM16(PWMV4_DUTY_POL_MASK, \
+ (v))
+/*
+ * [01:00] RW | PWM Mode
+ * 0 = One-shot mode, PWM generates waveform RPT times
+ * 1 = Continuous mode
+ * 2 = Capture mode, PWM measures cycles of input waveform
+ * 3 = Reserved
+ */
+#define PWMV4_MODE_ONESHOT 0x0U
+#define PWMV4_MODE_CONT 0x1U
+#define PWMV4_MODE_CAPTURE 0x2U
+#define PWMV4_MODE_MASK GENMASK(1, 0)
+#define PWMV4_MODE(v) FIELD_PREP_WM16(PWMV4_MODE_MASK, (v))
+#define PWMV4_CTRL_COM_FLAGS (PWMV4_INACTIVE_POL(PWMV4_POLARITY_N) | \
+ PWMV4_DUTY_POL(PWMV4_POLARITY_P) | \
+ PWMV4_CTRL_OUT_MODE(PWMV4_LEFT_ALIGNED) | \
+ PWMV4_CTRL_UNALIGNED(true))
+#define PWMV4_CTRL_CONT_FLAGS (PWMV4_MODE(PWMV4_MODE_CONT) | \
+ PWMV4_CTRL_COM_FLAGS)
+#define PWMV4_CTRL_CAP_FLAGS (PWMV4_MODE(PWMV4_MODE_CAPTURE) | \
+ PWMV4_CTRL_COM_FLAGS)
+
+#define PWMV4_REG_PERIOD 0x010
+/*
+ * PERIOD Register Description
+ * [31:00] RW | Period of the output waveform
+ * Constraints: should be even if CTRL_OUT_MODE is CENTRE_ALIGNED
+ */
+
+#define PWMV4_REG_DUTY 0x014
+/*
+ * DUTY Register Description
+ * [31:00] RW | Duty cycle of the output waveform
+ * Constraints: should be even if CTRL_OUT_MODE is CENTRE_ALIGNED
+ */
+
+#define PWMV4_REG_OFFSET 0x018
+/*
+ * OFFSET Register Description
+ * [31:00] RW | Offset of the output waveform, based on the PWM clock
+ * Constraints: 0 <= v <= (PERIOD - DUTY)
+ */
+
+#define PWMV4_REG_RPT 0x01C
+/*
+ * RPT Register Description
+ * [31:16] RW | Second dimensional of the effective number of waveform
+ * repetitions. Increases by one every first dimensional times.
+ * Value `n` means `n + 1` repetitions. The final number of
+ * repetitions of the waveform in one-shot mode is:
+ * `(first_dimensional + 1) * (second_dimensional + 1)`
+ * [15:00] RW | First dimensional of the effective number of waveform
+ * repetitions. Value `n` means `n + 1` repetitions.
+ */
+
+#define PWMV4_REG_FILTER_CTRL 0x020
+/*
+ * FILTER_CTRL Register Description
+ * [31:16] WO | Write Enable Mask for the lower half of the register
+ * Set bit `n` here to 1 if you wish to modify bit `n >> 16` in
+ * the same write operation
+ * [15:10] RO | Reserved
+ * [09:04] RW | Filter window number
+ * [03:01] RO | Reserved
+ * [00:00] RW | Filter Enable, 0 = disabled, 1 = enabled
+ */
+
+#define PWMV4_REG_CNT 0x024
+/*
+ * CNT Register Description
+ * [31:00] RO | Current value of the PWM Channel 0 counter in pwm clock cycles,
+ * 0 <= v <= 2^32-1
+ */
+
+#define PWMV4_REG_ENABLE_DELAY 0x028
+/*
+ * ENABLE_DELAY Register Description
+ * [31:16] RO | Reserved
+ * [15:00] RW | PWM enable delay, in an unknown unit but probably cycles
+ */
+
+#define PWMV4_REG_HPC 0x02C
+/*
+ * HPC Register Description
+ * [31:00] RW | Number of effective high polarity cycles of the input waveform
+ * in capture mode. Based on the PWM clock. 0 <= v <= 2^32-1
+ */
+
+#define PWMV4_REG_LPC 0x030
+/*
+ * LPC Register Description
+ * [31:00] RW | Number of effective low polarity cycles of the input waveform
+ * in capture mode. Based on the PWM clock. 0 <= v <= 2^32-1
+ */
+
+#define PWMV4_REG_BIPHASIC_CNT_CTRL0 0x040
+/*
+ * BIPHASIC_CNT_CTRL0 Register Description
+ * [31:16] WO | Write Enable Mask for the lower half of the register
+ * Set bit `n` here to 1 if you wish to modify bit `n >> 16` in
+ * the same write operation
+ * [15:10] RO | Reserved
+ * [09:09] RW | Biphasic Counter Phase Edge Selection for mode 0,
+ * 0 = rising edge (posedge), 1 = falling edge (negedge)
+ * [08:08] RW | Biphasic Counter Clock force enable, 1 = force enable
+ * [07:07] W1T | Synchronous Enable
+ * [06:06] W1T | Mode Switch
+ * 0 = Normal Mode, 1 = Switch timer clock and measured clock
+ * Constraints: "Biphasic Counter Mode" must be 0 if this is 1
+ * [05:03] RW | Biphasic Counter Mode
+ * 0x0 = Mode 0, 0x1 = Mode 1, 0x2 = Mode 2, 0x3 = Mode 3,
+ * 0x4 = Mode 4, 0x5 = Reserved
+ * [02:02] RW | Biphasic Counter Clock Selection
+ * 0 = clock is from PLL and frequency can be configured
+ * 1 = clock is from crystal oscillator and frequency is fixed
+ * [01:01] RW | Biphasic Counter Continuous Mode
+ * [00:00] W1T | Biphasic Counter Enable
+ */
+
+#define PWMV4_REG_BIPHASIC_CNT_CTRL1 0x044
+/*
+ * BIPHASIC_CNT_CTRL1 Register Description
+ * [31:16] WO | Write Enable Mask for the lower half of the register
+ * Set bit `n` here to 1 if you wish to modify bit `n >> 16` in
+ * the same write operation
+ * [15:11] RO | Reserved
+ * [10:04] RW | Biphasic Counter Filter Window Number
+ * [03:01] RO | Reserved
+ * [00:00] RW | Biphasic Counter Filter Enable
+ */
+
+#define PWMV4_REG_BIPHASIC_CNT_TIMER 0x048
+/*
+ * BIPHASIC_CNT_TIMER Register Description
+ * [31:00] RW | Biphasic Counter Timer Value, in number of biphasic counter
+ * timer clock cycles
+ */
+
+#define PWMV4_REG_BIPHASIC_CNT_RES 0x04C
+/*
+ * BIPHASIC_CNT_RES Register Description
+ * [31:00] RO | Biphasic Counter Result Value
+ * Constraints: Can only be read after INTSTS[9] is asserted
+ */
+
+#define PWMV4_REG_BIPHASIC_CNT_RES_S 0x050
+/*
+ * BIPHASIC_CNT_RES_S Register Description
+ * [31:00] RO | Biphasic Counter Result Value with synchronised processing
+ * Can be read in real-time if BIPHASIC_CNT_CTRL0[7] was set to 1
+ */
+
+#define PWMV4_REG_INTSTS 0x070
+/*
+ * INTSTS Register Description
+ * [31:10] RO | Reserved
+ * [09:09] W1C | Biphasic Counter Interrupt Status, 1 = interrupt asserted
+ * [08:08] W1C | Waveform Middle Interrupt Status, 1 = interrupt asserted
+ * [07:07] W1C | Waveform Max Interrupt Status, 1 = interrupt asserted
+ * [06:06] W1C | IR Transmission End Interrupt Status, 1 = interrupt asserted
+ * [05:05] W1C | Power Key Match Interrupt Status, 1 = interrupt asserted
+ * [04:04] W1C | Frequency Meter Interrupt Status, 1 = interrupt asserted
+ * [03:03] W1C | Reload Interrupt Status, 1 = interrupt asserted
+ * [02:02] W1C | Oneshot End Interrupt Status, 1 = interrupt asserted
+ * [01:01] W1C | HPC Capture Interrupt Status, 1 = interrupt asserted
+ * [00:00] W1C | LPC Capture Interrupt Status, 1 = interrupt asserted
+ */
+#define PWMV4_INT_LPC BIT(0)
+#define PWMV4_INT_HPC BIT(1)
+#define PWMV4_INT_LPC_W(v) FIELD_PREP_WM16(PWMV4_INT_LPC, \
+ ((v) ? 1 : 0))
+#define PWMV4_INT_HPC_W(v) FIELD_PREP_WM16(PWMV4_INT_HPC, \
+ ((v) ? 1 : 0))
+
+#define PWMV4_REG_INT_EN 0x074
+/*
+ * INT_EN Register Description
+ * [31:16] WO | Write Enable Mask for the lower half of the register
+ * Set bit `n` here to 1 if you wish to modify bit `n >> 16` in
+ * the same write operation
+ * [15:10] RO | Reserved
+ * [09:09] RW | Biphasic Counter Interrupt Enable, 1 = enabled
+ * [08:08] W1C | Waveform Middle Interrupt Enable, 1 = enabled
+ * [07:07] W1C | Waveform Max Interrupt Enable, 1 = enabled
+ * [06:06] W1C | IR Transmission End Interrupt Enable, 1 = enabled
+ * [05:05] W1C | Power Key Match Interrupt Enable, 1 = enabled
+ * [04:04] W1C | Frequency Meter Interrupt Enable, 1 = enabled
+ * [03:03] W1C | Reload Interrupt Enable, 1 = enabled
+ * [02:02] W1C | Oneshot End Interrupt Enable, 1 = enabled
+ * [01:01] W1C | HPC Capture Interrupt Enable, 1 = enabled
+ * [00:00] W1C | LPC Capture Interrupt Enable, 1 = enabled
+ */
+
+#define PWMV4_REG_INT_MASK 0x078
+/*
+ * INT_MASK Register Description
+ * [31:16] WO | Write Enable Mask for the lower half of the register
+ * Set bit `n` here to 1 if you wish to modify bit `n >> 16` in
+ * the same write operation
+ * [15:10] RO | Reserved
+ * [09:09] RW | Biphasic Counter Interrupt Masked, 1 = masked
+ * [08:08] W1C | Waveform Middle Interrupt Masked, 1 = masked
+ * [07:07] W1C | Waveform Max Interrupt Masked, 1 = masked
+ * [06:06] W1C | IR Transmission End Interrupt Masked, 1 = masked
+ * [05:05] W1C | Power Key Match Interrupt Masked, 1 = masked
+ * [04:04] W1C | Frequency Meter Interrupt Masked, 1 = masked
+ * [03:03] W1C | Reload Interrupt Masked, 1 = masked
+ * [02:02] W1C | Oneshot End Interrupt Masked, 1 = masked
+ * [01:01] W1C | HPC Capture Interrupt Masked, 1 = masked
+ * [00:00] W1C | LPC Capture Interrupt Masked, 1 = masked
+ */
+
+static inline u32 mfpwm_reg_read(void __iomem *base, u32 reg)
+{
+ return readl(base + reg);
+}
+
+static inline void mfpwm_reg_write(void __iomem *base, u32 reg, u32 val)
+{
+ writel(val, base + reg);
+}
+
+/**
+ * mfpwm_acquire - try becoming the active mfpwm function device
+ * @pwmf: pointer to the calling driver instance's &struct rockchip_mfpwm_func
+ *
+ * mfpwm device "function" drivers must call this function before doing anything
+ * that either modifies or relies on the parent device's state, such as clocks,
+ * enabling/disabling outputs, modifying shared regs etc.
+ *
+ * The return statues should always be checked.
+ *
+ * All mfpwm_acquire() calls must be balanced with corresponding mfpwm_release()
+ * calls once the device is no longer making changes that affect other devices,
+ * or stops producing user-visible effects that depend on the current device
+ * state being kept as-is. (e.g. after the PWM output signal is stopped)
+ *
+ * The same device function may mfpwm_acquire() multiple times while it already
+ * is active, i.e. it is re-entrant, though it needs to balance this with the
+ * same number of mfpwm_release() calls.
+ *
+ * Context: This function does not sleep.
+ *
+ * Return:
+ * * %0 - success
+ * * %-EBUSY - a different device function is active
+ * * %-EOVERFLOW - the acquire counter is at its maximum
+ */
+extern int __must_check mfpwm_acquire(struct rockchip_mfpwm_func *pwmf);
+
+/**
+ * mfpwm_release - drop usage of active mfpwm device function by 1
+ * @pwmf: pointer to the calling driver instance's &struct rockchip_mfpwm_func
+ *
+ * This is the balancing call to mfpwm_acquire(). If no users of the device
+ * function remain, set the mfpwm device to have no active device function,
+ * allowing other device functions to claim it.
+ */
+extern void mfpwm_release(const struct rockchip_mfpwm_func *pwmf);
+
+/**
+ * mfpwm_get_mode - get the current mode the hardware is in
+ * @pwmf: pointer to a &struct rockchip_mfpwm_func
+ *
+ * Check the hardware registers of the PWM hardware to determine which mode it
+ * is currently operating in, if any.
+ *
+ * Returns:
+ * - %-EINVAL if @pwmf is %NULL or an error pointer
+ * - %-1 if the PWM hardware is off, regardless of operating mode
+ * - %PWMV4_MODE_ONESHOT if PWM hardware is in one-shot output mode
+ * - %PWMV4_MODE_CONT if PWM hardware is in continuous output mode
+ * - %PWMV4_MODE_CAPTURE if PWM hardware is in capture mode
+ */
+extern int mfpwm_get_mode(const struct rockchip_mfpwm_func *pwmf);
+
+#endif /* __SOC_ROCKCHIP_MFPWM_H__ */
--
2.53.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 3/6] pwm: Add rockchip PWMv4 driver
2026-04-20 13:52 [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 1/6] dt-bindings: pwm: Add a new binding for rockchip,rk3576-pwm Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 2/6] mfd: Add Rockchip mfpwm driver Nicolas Frattaroli
@ 2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 4/6] counter: Add rockchip-pwm-capture driver Nicolas Frattaroli
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Nicolas Frattaroli @ 2026-04-20 13:52 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Lee Jones, William Breathitt Gray,
Damon Ding
Cc: Nicolas Frattaroli, kernel, Jonas Karlman, Alexey Charkov,
linux-rockchip, linux-pwm, devicetree, linux-arm-kernel,
linux-kernel, linux-iio
The Rockchip RK3576 brings with it a new PWM IP, in downstream code
referred to as "v4". This new IP is different enough from the previous
Rockchip IP that I felt it necessary to add a new driver for it, instead
of shoehorning it in the old one.
Add this new driver, based on the PWM core's waveform APIs. Its platform
device is registered by the parent mfpwm driver, from which it also
receives a little platform data struct, so that mfpwm can guarantee that
all the platform device drivers spread across different subsystems for
this specific hardware IP do not interfere with each other.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
MAINTAINERS | 1 +
drivers/pwm/Kconfig | 11 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-rockchip-v4.c | 383 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 396 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d52731242a33..68bb9ee07a47 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23179,6 +23179,7 @@ L: linux-pwm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pwm/rockchip,rk3576-pwm.yaml
F: drivers/mfd/rockchip-mfpwm.c
+F: drivers/pwm/pwm-rockchip-v4.c
F: include/linux/mfd/rockchip-mfpwm.h
ROCKCHIP RK3568 RANDOM NUMBER GENERATOR SUPPORT
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 6f3147518376..3fe7993bf12b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -625,6 +625,17 @@ config PWM_ROCKCHIP
Generic PWM framework driver for the PWM controller found on
Rockchip SoCs.
+config PWM_ROCKCHIP_V4
+ tristate "Rockchip PWM v4 support"
+ depends on MFD_ROCKCHIP_MFPWM
+ help
+ Generic PWM framework driver for the PWM controller found on
+ later Rockchip SoCs such as the RK3576.
+
+ Uses the Rockchip Multi-function PWM controller driver infrastructure
+ to guarantee fearlessly concurrent operation with other functions of
+ the same device implemented by drivers in other subsystems.
+
config PWM_SAMSUNG
tristate "Samsung PWM support"
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 0dc0d2b69025..a234027dbbc6 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_PWM_RENESAS_RZG2L_GPT) += pwm-rzg2l-gpt.o
obj-$(CONFIG_PWM_RENESAS_RZ_MTU3) += pwm-rz-mtu3.o
obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
+obj-$(CONFIG_PWM_ROCKCHIP_V4) += pwm-rockchip-v4.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
diff --git a/drivers/pwm/pwm-rockchip-v4.c b/drivers/pwm/pwm-rockchip-v4.c
new file mode 100644
index 000000000000..b7de72c433c5
--- /dev/null
+++ b/drivers/pwm/pwm-rockchip-v4.c
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ *
+ * A Pulse-Width-Modulation (PWM) generator driver for the generators found in
+ * Rockchip SoCs such as the RK3576, internally referred to as "PWM v4". Uses
+ * the MFPWM infrastructure to guarantee exclusive use over the device without
+ * other functions of the device from different drivers interfering with its
+ * operation while it's active.
+ *
+ * Technical Reference Manual: Chapter 31 of the RK3506 TRM Part 1, a SoC which
+ * uses the same PWM hardware and has a publicly available TRM.
+ * https://opensource.rock-chips.com/images/3/36/Rockchip_RK3506_TRM_Part_1_V1.2-20250811.pdf
+ *
+ * Authors:
+ * Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+ *
+ * Limitations:
+ * - The hardware supports both completing the currently running period
+ * on disable (by switching to oneshot mode with a single repetition and
+ * only disable when the complete irq fires), and abrupt disable (freeze).
+ * Only the latter is implemented in the driver.
+ * - When the output is disabled, the pin will remain driven to whatever state
+ * it last had.
+ * - Adjustments to the duty cycle will only take effect during the next period.
+ * - Adjustments to the period length will only take effect during the next
+ * period.
+ * - The hardware only supports offsets in [0, period - duty_cycle]
+ */
+
+#include <linux/math64.h>
+#include <linux/mfd/rockchip-mfpwm.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+
+struct rockchip_pwm_v4 {
+ struct rockchip_mfpwm_func *pwmf;
+ struct pwm_chip chip;
+};
+
+struct __packed rockchip_pwm_v4_wf {
+ u32 period;
+ u32 duty;
+ u32 offset;
+ unsigned long rate;
+};
+
+static inline struct rockchip_pwm_v4 *to_rockchip_pwm_v4(struct pwm_chip *chip)
+{
+ return pwmchip_get_drvdata(chip);
+}
+
+/**
+ * rockchip_pwm_v4_round_single - convert a PWM parameter to hardware
+ * @rate: clock rate of the PWM clock, as per clk_get_rate
+ * Assumed to be <= 1GHz for overflow considerations
+ * @in_val: parameter in nanoseconds to convert
+ *
+ * Returns the rounded value, saturating at U32_MAX if too large
+ */
+static u32 rockchip_pwm_v4_round_single(unsigned long rate, u64 in_val)
+{
+ u64 tmp;
+
+ tmp = mul_u64_u64_div_u64(rate, in_val, NSEC_PER_SEC);
+ if (tmp > U32_MAX)
+ tmp = U32_MAX;
+
+ return tmp;
+}
+
+/**
+ * rockchip_pwm_v4_round_params - convert PWM parameters to hardware
+ * @rate: PWM clock rate to do the calculations at
+ * @wf: pointer to the generic &struct pwm_waveform input parameters
+ * @wfhw: pointer to the hardware-specific &struct rockchip_pwm_v4_wf output
+ * parameters that the results will be stored in
+ *
+ * Convert nanosecond-based duty/period/offset parameters to the PWM hardware's
+ * native rounded representation in number of cycles at clock rate @rate. Should
+ * any of the input parameters be out of range for the hardware, the
+ * corresponding output parameter is the maximum permissible value for said
+ * parameter with considerations to the others.
+ */
+static void rockchip_pwm_v4_round_params(unsigned long rate,
+ const struct pwm_waveform *wf,
+ struct rockchip_pwm_v4_wf *wfhw)
+{
+ wfhw->period = rockchip_pwm_v4_round_single(rate, wf->period_length_ns);
+
+ wfhw->duty = rockchip_pwm_v4_round_single(rate, wf->duty_length_ns);
+
+ /* As per TRM, PWM_OFFSET: "The value ranges from 0 to (period-duty)" */
+ wfhw->offset = rockchip_pwm_v4_round_single(rate, wf->duty_offset_ns);
+ if (!wfhw->period) /* Don't underflow when pwm disabled */
+ wfhw->offset = 0;
+ else if (wfhw->offset > wfhw->period - wfhw->duty)
+ wfhw->offset = wfhw->period - wfhw->duty;
+}
+
+static int rockchip_pwm_v4_round_wf_tohw(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ const struct pwm_waveform *wf,
+ void *_wfhw)
+{
+ struct rockchip_pwm_v4 *pc = to_rockchip_pwm_v4(chip);
+ struct rockchip_pwm_v4_wf *wfhw = _wfhw;
+ unsigned long rate;
+
+ rate = clk_get_rate(pc->pwmf->core);
+
+ /*
+ * It's unlikely this code path is ever taken, as current hardware does
+ * not expose a clock that comes anywhere close to 1GHz. However, in
+ * order to avoid even a theoretical overflow in parameter rounding,
+ * error out if this ever happens to be the case.
+ */
+ if (rate > NSEC_PER_SEC)
+ return -ERANGE;
+
+ rockchip_pwm_v4_round_params(rate, wf, wfhw);
+
+ if (wf->period_length_ns > 0)
+ wfhw->rate = rate;
+ else
+ wfhw->rate = 0;
+
+ dev_dbg(&chip->dev,
+ "tohw: pwm#%u: %lld/%lld [+%lld] @%lu -> DUTY: %08x, PERIOD: %08x, OFFSET: %08x\n",
+ pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
+ rate, wfhw->duty, wfhw->period, wfhw->offset);
+
+ return 0;
+}
+
+static int rockchip_pwm_v4_round_wf_fromhw(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ const void *_wfhw,
+ struct pwm_waveform *wf)
+{
+ const struct rockchip_pwm_v4_wf *wfhw = _wfhw;
+ unsigned long rate = wfhw->rate;
+
+ if (rate) {
+ wf->period_length_ns = DIV_ROUND_UP((u64)wfhw->period * NSEC_PER_SEC, rate);
+ wf->duty_length_ns = DIV_ROUND_UP((u64)wfhw->duty * NSEC_PER_SEC, rate);
+ wf->duty_offset_ns = DIV_ROUND_UP((u64)wfhw->offset * NSEC_PER_SEC, rate);
+ } else {
+ wf->period_length_ns = 0;
+ wf->duty_length_ns = 0;
+ wf->duty_offset_ns = 0;
+ }
+
+ dev_dbg(&chip->dev,
+ "fromhw: pwm#%u: DUTY: %08x, PERIOD: %08x, OFFSET: %08x @%lu -> %lld/%lld [+%lld]\n",
+ pwm->hwpwm, wfhw->duty, wfhw->period, wfhw->offset, rate,
+ wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns);
+
+ return 0;
+}
+
+static int rockchip_pwm_v4_read_wf(struct pwm_chip *chip, struct pwm_device *pwm,
+ void *_wfhw)
+{
+ struct rockchip_pwm_v4 *pc = to_rockchip_pwm_v4(chip);
+ struct rockchip_pwm_v4_wf *wfhw = _wfhw;
+ unsigned long rate;
+ int ret;
+
+ ret = mfpwm_acquire(pc->pwmf);
+ if (ret)
+ return ret;
+
+ rate = clk_get_rate(pc->pwmf->core);
+
+ wfhw->period = mfpwm_reg_read(pc->pwmf->base, PWMV4_REG_PERIOD);
+ wfhw->duty = mfpwm_reg_read(pc->pwmf->base, PWMV4_REG_DUTY);
+ wfhw->offset = mfpwm_reg_read(pc->pwmf->base, PWMV4_REG_OFFSET);
+ if (rockchip_pwm_v4_is_enabled(mfpwm_reg_read(pc->pwmf->base, PWMV4_REG_ENABLE)))
+ wfhw->rate = rate;
+ else
+ wfhw->rate = 0;
+
+ mfpwm_release(pc->pwmf);
+
+ return 0;
+}
+
+static int rockchip_pwm_v4_write_wf(struct pwm_chip *chip, struct pwm_device *pwm,
+ const void *_wfhw)
+{
+ struct rockchip_pwm_v4 *pc = to_rockchip_pwm_v4(chip);
+ const struct rockchip_pwm_v4_wf *wfhw = _wfhw;
+ bool was_enabled;
+ int ret;
+
+ ret = mfpwm_acquire(pc->pwmf);
+ if (ret)
+ return ret;
+
+ was_enabled = rockchip_pwm_v4_is_enabled(mfpwm_reg_read(pc->pwmf->base,
+ PWMV4_REG_ENABLE));
+
+ /*
+ * "But Nicolas", you ask with valid concerns, "why would you enable the
+ * PWM before setting all the parameter registers?"
+ *
+ * Excellent question, Mr. Reader M. Strawman! The RK3576 TRM Part 1
+ * Section 34.6.3 specifies that this is the intended order of writes.
+ * Doing the PWM_EN and PWM_CLK_EN writes after the params but before
+ * the CTRL_UPDATE_EN, or even after the CTRL_UPDATE_EN, results in
+ * erratic behaviour where repeated turning on and off of the PWM may
+ * not turn it off under all circumstances. This is also why we don't
+ * use relaxed writes; it's not worth the footgun.
+ */
+ if (wfhw->rate)
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_ENABLE,
+ FIELD_PREP_WM16(PWMV4_EN_BOTH_MASK,
+ PWMV4_EN_BOTH_MASK));
+ else
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_ENABLE,
+ FIELD_PREP_WM16(PWMV4_EN_BOTH_MASK, 0));
+
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_PERIOD, wfhw->period);
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_DUTY, wfhw->duty);
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_OFFSET, wfhw->offset);
+
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_CTRL, PWMV4_CTRL_CONT_FLAGS);
+
+ /* Commit new configuration to hardware output. */
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_ENABLE,
+ PWMV4_CTRL_UPDATE_EN);
+
+ if (wfhw->rate) {
+ if (!was_enabled) {
+ dev_dbg(&chip->dev, "Enabling PWM output\n");
+ ret = clk_enable(pc->pwmf->core);
+ if (ret)
+ goto err_mfpwm_release;
+ ret = clk_set_rate_exclusive(pc->pwmf->core, wfhw->rate);
+ if (ret) {
+ clk_disable(pc->pwmf->core);
+ goto err_mfpwm_release;
+ }
+
+ /*
+ * Output should be on now, acquire device to guarantee
+ * exclusion with other device functions while it's on.
+ *
+ * It's highly unlikely that this fails, as mfpwm has
+ * already been acquired before, and this is just a
+ * usage counter increase. Not worth the added
+ * complexity of clearing the PWMV4_REG_ENABLE again,
+ * especially considering the CTRL_UPDATE_EN behaviour.
+ */
+ ret = mfpwm_acquire(pc->pwmf);
+ if (ret) {
+ clk_rate_exclusive_put(pc->pwmf->core);
+ clk_disable(pc->pwmf->core);
+ goto err_mfpwm_release;
+ }
+ }
+ } else if (was_enabled) {
+ dev_dbg(&chip->dev, "Disabling PWM output\n");
+ clk_rate_exclusive_put(pc->pwmf->core);
+ clk_disable(pc->pwmf->core);
+ /* Output is off now, extra release to balance extra acquire */
+ mfpwm_release(pc->pwmf);
+ }
+
+err_mfpwm_release:
+ mfpwm_release(pc->pwmf);
+
+ return ret;
+}
+
+static const struct pwm_ops rockchip_pwm_v4_ops = {
+ .sizeof_wfhw = sizeof(struct rockchip_pwm_v4_wf),
+ .round_waveform_tohw = rockchip_pwm_v4_round_wf_tohw,
+ .round_waveform_fromhw = rockchip_pwm_v4_round_wf_fromhw,
+ .read_waveform = rockchip_pwm_v4_read_wf,
+ .write_waveform = rockchip_pwm_v4_write_wf,
+};
+
+static bool rockchip_pwm_v4_on_and_continuous(struct rockchip_pwm_v4 *pc)
+{
+ bool en;
+ u32 val;
+
+ en = rockchip_pwm_v4_is_enabled(mfpwm_reg_read(pc->pwmf->base,
+ PWMV4_REG_ENABLE));
+ val = mfpwm_reg_read(pc->pwmf->base, PWMV4_REG_CTRL);
+
+ return en && ((val & PWMV4_MODE_MASK) == PWMV4_MODE_CONT);
+}
+
+static int rockchip_pwm_v4_probe(struct platform_device *pdev)
+{
+ struct rockchip_mfpwm_func *pwmf = dev_get_platdata(&pdev->dev);
+ struct rockchip_pwm_v4 *pc;
+ struct pwm_chip *chip;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ /*
+ * For referencing the PWM in the DT to work, we need the parent MFD
+ * device's OF node.
+ */
+ dev->of_node_reused = true;
+ device_set_node(dev, of_fwnode_handle(dev->parent->of_node));
+
+ chip = devm_pwmchip_alloc(dev, 1, sizeof(*pc));
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+
+ pc = to_rockchip_pwm_v4(chip);
+ pc->pwmf = pwmf;
+
+ ret = mfpwm_acquire(pwmf);
+ if (ret)
+ return dev_err_probe(dev, ret, "Couldn't acquire mfpwm in probe\n");
+
+ if (!rockchip_pwm_v4_on_and_continuous(pc))
+ mfpwm_release(pwmf);
+ else {
+ dev_dbg(dev, "PWM was already on at probe time\n");
+ ret = clk_enable(pwmf->core);
+ if (ret) {
+ dev_err_probe(dev, ret, "Enabling pwm clock failed\n");
+ goto err_mfpwm_release;
+ }
+ ret = clk_rate_exclusive_get(pc->pwmf->core);
+ if (ret) {
+ dev_err_probe(dev, ret, "Protecting pwm clock failed\n");
+ goto err_clk_disable;
+ }
+ }
+
+ platform_set_drvdata(pdev, chip);
+
+ chip->ops = &rockchip_pwm_v4_ops;
+
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to add PWM chip\n");
+ if (rockchip_pwm_v4_on_and_continuous(pc))
+ goto err_rate_put;
+
+ return ret;
+ }
+
+ return 0;
+
+err_rate_put:
+ clk_rate_exclusive_put(pwmf->core);
+err_clk_disable:
+ clk_disable(pwmf->core);
+err_mfpwm_release:
+ mfpwm_release(pwmf);
+
+ return ret;
+}
+
+static const struct platform_device_id rockchip_pwm_v4_ids[] = {
+ { .name = "rockchip-pwm-v4", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, rockchip_pwm_v4_ids);
+
+static struct platform_driver rockchip_pwm_v4_driver = {
+ .probe = rockchip_pwm_v4_probe,
+ .driver = {
+ .name = "rockchip-pwm-v4",
+ },
+ .id_table = rockchip_pwm_v4_ids,
+};
+module_platform_driver(rockchip_pwm_v4_driver);
+
+MODULE_AUTHOR("Nicolas Frattaroli <nicolas.frattaroli@collabora.com>");
+MODULE_DESCRIPTION("Rockchip PWMv4 Driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("ROCKCHIP_MFPWM");
+MODULE_ALIAS("platform:pwm-rockchip-v4");
--
2.53.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 4/6] counter: Add rockchip-pwm-capture driver
2026-04-20 13:52 [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Nicolas Frattaroli
` (2 preceding siblings ...)
2026-04-20 13:52 ` [PATCH v5 3/6] pwm: Add rockchip PWMv4 driver Nicolas Frattaroli
@ 2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 5/6] arm64: dts: rockchip: add PWM nodes to RK3576 SoC dtsi Nicolas Frattaroli
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Nicolas Frattaroli @ 2026-04-20 13:52 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Lee Jones, William Breathitt Gray,
Damon Ding
Cc: Nicolas Frattaroli, kernel, Jonas Karlman, Alexey Charkov,
linux-rockchip, linux-pwm, devicetree, linux-arm-kernel,
linux-kernel, linux-iio
Among many other things, Rockchip's new PWMv4 IP in the RK3576 supports
PWM capture functionality.
Add a basic driver for this that works to expose HPC/LPC counts and
state change events to userspace through the counter framework. It's
quite basic, but works well enough to demonstrate the device function
exclusion stuff that mfpwm does, in order to eventually support all the
functions of this device in drivers within their appropriate subsystems,
without them interfering with each other.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
MAINTAINERS | 1 +
drivers/counter/Kconfig | 11 ++
drivers/counter/Makefile | 1 +
drivers/counter/rockchip-pwm-capture.c | 307 +++++++++++++++++++++++++++++++++
4 files changed, 320 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 68bb9ee07a47..3f72784dd5bc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23178,6 +23178,7 @@ L: linux-rockchip@lists.infradead.org
L: linux-pwm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pwm/rockchip,rk3576-pwm.yaml
+F: drivers/counter/rockchip-pwm-capture.c
F: drivers/mfd/rockchip-mfpwm.c
F: drivers/pwm/pwm-rockchip-v4.c
F: include/linux/mfd/rockchip-mfpwm.h
diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig
index d30d22dfe577..85adeb41aeed 100644
--- a/drivers/counter/Kconfig
+++ b/drivers/counter/Kconfig
@@ -90,6 +90,17 @@ config MICROCHIP_TCB_CAPTURE
To compile this driver as a module, choose M here: the
module will be called microchip-tcb-capture.
+config ROCKCHIP_PWM_CAPTURE
+ tristate "Rockchip PWM Counter Capture driver"
+ depends on MFD_ROCKCHIP_MFPWM
+ help
+ Generic counter framework driver for the multi-function PWM on
+ Rockchip SoCs such as the RK3576.
+
+ Uses the Rockchip Multi-function PWM controller driver infrastructure
+ to guarantee exclusive operation with other functions of the same
+ device implemented by drivers in other subsystems.
+
config RZ_MTU3_CNT
tristate "Renesas RZ/G2L MTU3a counter driver"
depends on RZ_MTU3
diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile
index fa3c1d08f706..2bfcfc2c584b 100644
--- a/drivers/counter/Makefile
+++ b/drivers/counter/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_FTM_QUADDEC) += ftm-quaddec.o
obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) += microchip-tcb-capture.o
obj-$(CONFIG_INTEL_QEP) += intel-qep.o
obj-$(CONFIG_TI_ECAP_CAPTURE) += ti-ecap-capture.o
+obj-$(CONFIG_ROCKCHIP_PWM_CAPTURE) += rockchip-pwm-capture.o
diff --git a/drivers/counter/rockchip-pwm-capture.c b/drivers/counter/rockchip-pwm-capture.c
new file mode 100644
index 000000000000..09a92f2bc409
--- /dev/null
+++ b/drivers/counter/rockchip-pwm-capture.c
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ *
+ * A counter driver for the Pulse-Width-Modulation (PWM) hardware found on
+ * Rockchip SoCs such as the RK3576, internally referred to as "PWM v4". It
+ * allows for measuring the high cycles and low cycles of a PWM signal through
+ * the generic counter framework, while guaranteeing exclusive use over the
+ * MFPWM device while the counter is enabled.
+ *
+ * Authors:
+ * Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+ */
+
+#include <linux/cleanup.h>
+#include <linux/counter.h>
+#include <linux/devm-helpers.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/rockchip-mfpwm.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#define RKPWMC_INT_MASK (PWMV4_INT_LPC | PWMV4_INT_HPC)
+
+struct rockchip_pwm_capture {
+ struct rockchip_mfpwm_func *pwmf;
+ struct counter_device *counter;
+};
+
+static struct counter_signal rkpwmc_signals[] = {
+ {
+ .id = 0,
+ .name = "PWM Clock"
+ },
+};
+
+static const enum counter_synapse_action rkpwmc_hpc_lpc_actions[] = {
+ COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
+ COUNTER_SYNAPSE_ACTION_NONE,
+};
+
+static struct counter_synapse rkpwmc_pwm_synapses[] = {
+ {
+ .actions_list = rkpwmc_hpc_lpc_actions,
+ .num_actions = ARRAY_SIZE(rkpwmc_hpc_lpc_actions),
+ .signal = &rkpwmc_signals[0]
+ },
+};
+
+static const enum counter_function rkpwmc_functions[] = {
+ COUNTER_FUNCTION_INCREASE,
+};
+
+static inline bool rkpwmc_is_enabled(struct rockchip_mfpwm_func *pwmf)
+{
+ return mfpwm_get_mode(pwmf) == PWMV4_MODE_CAPTURE;
+}
+
+static bool rkpwmc_acquire_if_enabled(struct rockchip_pwm_capture *pc)
+{
+ int ret;
+
+ ret = mfpwm_acquire(pc->pwmf);
+ if (ret < 0)
+ return false;
+
+ if (rkpwmc_is_enabled(pc->pwmf))
+ return true;
+
+ mfpwm_release(pc->pwmf);
+
+ return false;
+}
+
+static int rkpwmc_enable_read(struct counter_device *counter,
+ struct counter_count *count,
+ u8 *enable)
+{
+ struct rockchip_pwm_capture *pc = counter_priv(counter);
+
+ *enable = rkpwmc_is_enabled(pc->pwmf);
+
+ return 0;
+}
+
+static int rkpwmc_enable_write(struct counter_device *counter,
+ struct counter_count *count,
+ u8 enable)
+{
+ struct rockchip_pwm_capture *pc = counter_priv(counter);
+ int ret;
+
+ ret = mfpwm_acquire(pc->pwmf);
+ if (ret)
+ return ret;
+
+ if (!!enable != rkpwmc_is_enabled(pc->pwmf)) {
+ if (enable) {
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_ENABLE,
+ PWMV4_EN(false));
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_CTRL,
+ PWMV4_CTRL_CAP_FLAGS);
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_INT_EN,
+ PWMV4_INT_LPC_W(true) |
+ PWMV4_INT_HPC_W(true));
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_ENABLE,
+ PWMV4_EN(true) | PWMV4_CLK_EN(true));
+
+ ret = clk_enable(pc->pwmf->core);
+ if (ret)
+ goto err_release;
+
+ ret = clk_rate_exclusive_get(pc->pwmf->core);
+ if (ret)
+ goto err_disable_pwm_clk;
+
+ ret = mfpwm_acquire(pc->pwmf);
+ if (ret)
+ goto err_unprotect_pwm_clk;
+ } else {
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_INT_EN,
+ PWMV4_INT_LPC_W(false) |
+ PWMV4_INT_HPC_W(false));
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_ENABLE,
+ PWMV4_EN(false) | PWMV4_CLK_EN(false));
+ clk_rate_exclusive_put(pc->pwmf->core);
+ clk_disable(pc->pwmf->core);
+ mfpwm_release(pc->pwmf);
+ }
+ }
+
+ mfpwm_release(pc->pwmf);
+
+ return 0;
+
+err_unprotect_pwm_clk:
+ clk_rate_exclusive_put(pc->pwmf->core);
+err_disable_pwm_clk:
+ clk_disable(pc->pwmf->core);
+err_release:
+ mfpwm_release(pc->pwmf);
+
+ return ret;
+}
+
+static struct counter_comp rkpwmc_ext[] = {
+ COUNTER_COMP_ENABLE(rkpwmc_enable_read, rkpwmc_enable_write),
+};
+
+enum rkpwmc_count_id {
+ COUNT_LPC = 0,
+ COUNT_HPC = 1,
+};
+
+static struct counter_count rkpwmc_counts[] = {
+ {
+ .id = COUNT_LPC,
+ .name = "Low Polarity Capture",
+ .functions_list = rkpwmc_functions,
+ .num_functions = ARRAY_SIZE(rkpwmc_functions),
+ .synapses = rkpwmc_pwm_synapses,
+ .num_synapses = ARRAY_SIZE(rkpwmc_pwm_synapses),
+ .ext = rkpwmc_ext,
+ .num_ext = ARRAY_SIZE(rkpwmc_ext),
+ },
+ {
+ .id = COUNT_HPC,
+ .name = "High Polarity Capture",
+ .functions_list = rkpwmc_functions,
+ .num_functions = ARRAY_SIZE(rkpwmc_functions),
+ .synapses = rkpwmc_pwm_synapses,
+ .num_synapses = ARRAY_SIZE(rkpwmc_pwm_synapses),
+ .ext = rkpwmc_ext,
+ .num_ext = ARRAY_SIZE(rkpwmc_ext),
+ },
+};
+
+static int rkpwmc_count_read(struct counter_device *counter,
+ struct counter_count *count, u64 *value)
+{
+ struct rockchip_pwm_capture *pc = counter_priv(counter);
+
+ switch (count->id) {
+ case COUNT_LPC:
+ if (rkpwmc_acquire_if_enabled(pc)) {
+ *value = mfpwm_reg_read(pc->pwmf->base, PWMV4_REG_LPC);
+ mfpwm_release(pc->pwmf);
+ } else {
+ *value = 0;
+ }
+ return 0;
+ case COUNT_HPC:
+ if (rkpwmc_acquire_if_enabled(pc)) {
+ *value = mfpwm_reg_read(pc->pwmf->base, PWMV4_REG_HPC);
+ mfpwm_release(pc->pwmf);
+ } else {
+ *value = 0;
+ }
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct counter_ops rkpwmc_ops = {
+ .count_read = rkpwmc_count_read,
+};
+
+static irqreturn_t rkpwmc_irq_handler(int irq, void *data)
+{
+ struct rockchip_pwm_capture *pc = data;
+ u32 intsts;
+ u32 clr = 0;
+
+ intsts = mfpwm_reg_read(pc->pwmf->base, PWMV4_REG_INTSTS);
+
+ if (!(intsts & RKPWMC_INT_MASK))
+ return IRQ_NONE;
+
+ if (intsts & PWMV4_INT_LPC) {
+ clr |= PWMV4_INT_LPC;
+ counter_push_event(pc->counter, COUNTER_EVENT_CHANGE_OF_STATE, 0);
+ }
+
+ if (intsts & PWMV4_INT_HPC) {
+ clr |= PWMV4_INT_HPC;
+ counter_push_event(pc->counter, COUNTER_EVENT_CHANGE_OF_STATE, 1);
+ }
+
+ if (clr)
+ mfpwm_reg_write(pc->pwmf->base, PWMV4_REG_INTSTS, clr);
+
+ /* If other interrupt status bits are set, they're not for this driver */
+ if (intsts != clr)
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+
+static int rockchip_pwm_capture_probe(struct platform_device *pdev)
+{
+ struct rockchip_mfpwm_func *pwmf = dev_get_platdata(&pdev->dev);
+ struct rockchip_pwm_capture *pc;
+ struct counter_device *counter;
+ int ret;
+
+ /* Set our (still unset) OF node to the parent MFD device's OF node */
+ pdev->dev.parent->of_node_reused = true;
+ device_set_node(&pdev->dev,
+ of_fwnode_handle(no_free_ptr(pdev->dev.parent->of_node)));
+
+ counter = devm_counter_alloc(&pdev->dev, sizeof(*pc));
+ if (IS_ERR(counter))
+ return PTR_ERR(counter);
+
+ pc = counter_priv(counter);
+ pc->pwmf = pwmf;
+
+ platform_set_drvdata(pdev, pc);
+
+ /* If the counter is on at module probe, acquire it */
+ rkpwmc_acquire_if_enabled(pc);
+
+ counter->name = pdev->name;
+ counter->signals = rkpwmc_signals;
+ counter->num_signals = ARRAY_SIZE(rkpwmc_signals);
+ counter->ops = &rkpwmc_ops;
+ counter->counts = rkpwmc_counts;
+ counter->num_counts = ARRAY_SIZE(rkpwmc_counts);
+
+ pc->counter = counter;
+
+ ret = devm_counter_add(&pdev->dev, counter);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret, "Failed to add counter\n");
+
+ ret = devm_request_irq(&pdev->dev, pwmf->irq, rkpwmc_irq_handler,
+ IRQF_SHARED, pdev->name, pc);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Failed requesting IRQ\n");
+
+ return 0;
+}
+
+static const struct platform_device_id rockchip_pwm_capture_id_table[] = {
+ { .name = "rockchip-pwm-capture", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(platform, rockchip_pwm_capture_id_table);
+
+static struct platform_driver rockchip_pwm_capture_driver = {
+ .probe = rockchip_pwm_capture_probe,
+ .id_table = rockchip_pwm_capture_id_table,
+ .driver = {
+ .name = "rockchip-pwm-capture",
+ },
+};
+module_platform_driver(rockchip_pwm_capture_driver);
+
+MODULE_AUTHOR("Nicolas Frattaroli <nicolas.frattaroli@collabora.com>");
+MODULE_DESCRIPTION("Rockchip PWM Counter Capture Driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("ROCKCHIP_MFPWM");
+MODULE_IMPORT_NS("COUNTER");
+MODULE_ALIAS("platform:rockchip-pwm-capture");
--
2.53.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 5/6] arm64: dts: rockchip: add PWM nodes to RK3576 SoC dtsi
2026-04-20 13:52 [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Nicolas Frattaroli
` (3 preceding siblings ...)
2026-04-20 13:52 ` [PATCH v5 4/6] counter: Add rockchip-pwm-capture driver Nicolas Frattaroli
@ 2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 6/6] arm64: dts: rockchip: Add cooling fan to ROCK 4D Nicolas Frattaroli
2026-04-21 15:56 ` [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Jonathan Cameron
6 siblings, 0 replies; 8+ messages in thread
From: Nicolas Frattaroli @ 2026-04-20 13:52 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Lee Jones, William Breathitt Gray,
Damon Ding
Cc: Nicolas Frattaroli, kernel, Jonas Karlman, Alexey Charkov,
linux-rockchip, linux-pwm, devicetree, linux-arm-kernel,
linux-kernel, linux-iio
The RK3576 SoC features three distinct PWM controllers, with variable
numbers of channels. Add each channel as a separate node to the SoC's
device tree, as they don't really overlap in register ranges.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 208 +++++++++++++++++++++++++++++++
1 file changed, 208 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index e12a2a0cfb89..55d6b103c329 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1032,6 +1032,32 @@ uart1: serial@27310000 {
status = "disabled";
};
+ pwm0_2ch_0: pwm@27330000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x27330000 0x0 0x1000>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,
+ <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0m0_ch0>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm0_2ch_1: pwm@27331000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x27331000 0x0 0x1000>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,
+ <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0m0_ch1>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
pmu: power-management@27380000 {
compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
reg = <0x0 0x27380000 0x0 0x800>;
@@ -2630,6 +2656,188 @@ uart9: serial@2adc0000 {
status = "disabled";
};
+ pwm1_6ch_0: pwm@2add0000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2add0000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
+ <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1m0_ch0>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1_6ch_1: pwm@2add1000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2add1000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
+ <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1m0_ch1>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1_6ch_2: pwm@2add2000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2add2000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
+ <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1m0_ch2>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1_6ch_3: pwm@2add3000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2add3000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
+ <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1m0_ch3>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1_6ch_4: pwm@2add4000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2add4000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
+ <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1m0_ch4>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1_6ch_5: pwm@2add5000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2add5000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
+ <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1m0_ch5>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2_8ch_0: pwm@2ade0000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2ade0000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
+ <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_ch0>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2_8ch_1: pwm@2ade1000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2ade1000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
+ <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_ch1>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2_8ch_2: pwm@2ade2000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2ade2000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
+ <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_ch2>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2_8ch_3: pwm@2ade3000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2ade3000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
+ <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_ch3>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2_8ch_4: pwm@2ade4000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2ade4000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
+ <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_ch4>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2_8ch_5: pwm@2ade5000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2ade5000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
+ <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_ch5>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2_8ch_6: pwm@2ade6000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2ade6000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
+ <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_ch6>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2_8ch_7: pwm@2ade7000 {
+ compatible = "rockchip,rk3576-pwm";
+ reg = <0x0 0x2ade7000 0x0 0x1000>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
+ <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
+ clock-names = "pwm", "pclk", "osc", "rc";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_ch7>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
saradc: adc@2ae00000 {
compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
reg = <0x0 0x2ae00000 0x0 0x10000>;
--
2.53.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 6/6] arm64: dts: rockchip: Add cooling fan to ROCK 4D
2026-04-20 13:52 [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Nicolas Frattaroli
` (4 preceding siblings ...)
2026-04-20 13:52 ` [PATCH v5 5/6] arm64: dts: rockchip: add PWM nodes to RK3576 SoC dtsi Nicolas Frattaroli
@ 2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-21 15:56 ` [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Jonathan Cameron
6 siblings, 0 replies; 8+ messages in thread
From: Nicolas Frattaroli @ 2026-04-20 13:52 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Lee Jones, William Breathitt Gray,
Damon Ding
Cc: Nicolas Frattaroli, kernel, Jonas Karlman, Alexey Charkov,
linux-rockchip, linux-pwm, devicetree, linux-arm-kernel,
linux-kernel, linux-iio
The ROCK 4D has a header to connect a small cooling fan. This fan is
driven by one of the SoC's PWM outputs driving a transistor, that in
turn controls the fan's power.
With the introduction of PWM support, add a description of this cooling
fan, as well as the additional trips and cooling-maps for it.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 50 +++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
index 899a84b1fbf9..2d5ede010ad0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
@@ -45,6 +45,14 @@ rfkill {
shutdown-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
};
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 180 205 230 255>;
+ fan-supply = <&vcc_5v0_sys>;
+ pwms = <&pwm2_8ch_5 0 60000 0>;
+ #cooling-cells = <2>;
+ };
+
leds: leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -711,6 +719,36 @@ rgmii_phy0: ethernet-phy@1 {
};
};
+&package_thermal {
+ polling-delay = <100>;
+
+ trips {
+ package_fan0: package-fan0 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ package_fan1: package-fan1 {
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&package_fan0>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map2 {
+ trip = <&package_fan1>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset>;
@@ -720,6 +758,13 @@ &pcie0 {
};
&pinctrl {
+ fan {
+ fan_pwm: fan-pwm {
+ rockchip,pins =
+ <4 RK_PC5 14 &pcfg_pull_down_drv_level_5>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -770,6 +815,11 @@ wifi_en_h: wifi-en-h {
};
};
+&pwm2_8ch_5 {
+ pinctrl-0 = <&fan_pwm>;
+ status = "okay";
+};
+
&sai6 {
status = "okay";
};
--
2.53.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM
2026-04-20 13:52 [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Nicolas Frattaroli
` (5 preceding siblings ...)
2026-04-20 13:52 ` [PATCH v5 6/6] arm64: dts: rockchip: Add cooling fan to ROCK 4D Nicolas Frattaroli
@ 2026-04-21 15:56 ` Jonathan Cameron
6 siblings, 0 replies; 8+ messages in thread
From: Jonathan Cameron @ 2026-04-21 15:56 UTC (permalink / raw)
To: Nicolas Frattaroli
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Lee Jones, William Breathitt Gray,
Damon Ding, kernel, Jonas Karlman, Alexey Charkov, linux-rockchip,
linux-pwm, devicetree, linux-arm-kernel, linux-kernel, linux-iio,
Conor Dooley
On Mon, 20 Apr 2026 15:52:37 +0200
Nicolas Frattaroli <nicolas.frattaroli@collabora.com> wrote:
> This series introduces support for some of the functions of the new PWM
> silicon found on Rockchip's RK3576 SoC. Due to the wide range of
> functionalities offered by it, including many parts which this series'
> first iteration does not attempt to implement for now. The drivers are
> modelled as an MFD, with no leakage of the MFD-ness into the binding, as
> it's a Linux implementation detail.
Just thought I'd point out that as this includes the linux-iio
list sashiko took a look at it. Quite a few things and at least
the first one I looked at was valid (a dereference before a validity
check)
https://sashiko.dev/#/patchset/20260420-rk3576-pwm-v5-0-ae7cfbbe5427%40collabora.com
Whilst this tool does generate some false positives, it also finds
quite a few things it seems us humans fail to spot.
Jonathan
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