[PATCH 0/2] iio: adc: ad4080: add backend data size configuration

[PATCH 0/2] iio: adc: ad4080: add backend data size configuration

[Antoniu Miclaus]

The AD408X AXI core can pack sample data on the bus using different word
widths (20-bit, 16-bit and 14-bit), selected through the packet format
field of the CNTRL_3 register. Until now this was left at its default,
which only matched the AD4080 20-bit resolution.

This series exposes the packet format through a new data_size_set backend
operation and has the ad4080 driver program it during channel setup based
on the channel resolution, so the bus packing always matches the device
realbits.

Patch 1 adds the data_size_set operation to the adi-axi-adc backend.
Patch 2 calls iio_backend_data_size_set() from the ad4080 channel setup.

Link: https://analogdevicesinc.github.io/hdl/library/axi_ad408x/index.html

Antoniu Miclaus (2):
  iio: adc: adi-axi-adc: add data size support for AD408X backend
  iio: adc: ad4080: configure backend data size

 drivers/iio/adc/ad4080.c      |  5 +++++
 drivers/iio/adc/adi-axi-adc.c | 30 ++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+)

-- 
2.43.0

[PATCH 1/2] iio: adc: adi-axi-adc: add data size support for AD408X backend

[Antoniu Miclaus]

The AD408X AXI core can pack the sample data on the bus using different
word widths. Expose this through the data_size_set backend operation so
that frontends can program the packet format field (bits 3:2 of the
CNTRL_3 register) according to the ADC resolution: 20-bit, 16-bit and
14-bit map to packet format values 0, 1 and 2 respectively.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 drivers/iio/adc/adi-axi-adc.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c
index ced0a2321ecf..aac6f4a0705e 100644
--- a/drivers/iio/adc/adi-axi-adc.c
+++ b/drivers/iio/adc/adi-axi-adc.c
@@ -54,6 +54,10 @@
 #define   AXI_AD485X_PACKET_FORMAT_24BIT	0x1
 #define   AXI_AD485X_PACKET_FORMAT_32BIT	0x2
 #define   AXI_AD408X_CNTRL_3_FILTER_EN_MSK	BIT(0)
+#define   AXI_AD408X_CNTRL_3_PACKET_FORMAT_MSK	GENMASK(3, 2)
+#define   AXI_AD408X_PACKET_FORMAT_20BIT	0x0
+#define   AXI_AD408X_PACKET_FORMAT_16BIT	0x1
+#define   AXI_AD408X_PACKET_FORMAT_14BIT	0x2
 
 #define ADI_AXI_ADC_REG_SYNC_STATUS		0x0068
 #define   ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK	BIT(0)
@@ -437,6 +441,31 @@ static int axi_adc_ad408x_filter_type_set(struct iio_backend *back,
 				 AXI_AD408X_CNTRL_3_FILTER_EN_MSK);
 }
 
+static int axi_adc_ad408x_data_size_set(struct iio_backend *back,
+					unsigned int size)
+{
+	struct adi_axi_adc_state *st = iio_backend_get_priv(back);
+	unsigned int val;
+
+	switch (size) {
+	case 20:
+		val = AXI_AD408X_PACKET_FORMAT_20BIT;
+		break;
+	case 16:
+		val = AXI_AD408X_PACKET_FORMAT_16BIT;
+		break;
+	case 14:
+		val = AXI_AD408X_PACKET_FORMAT_14BIT;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
+				  AXI_AD408X_CNTRL_3_PACKET_FORMAT_MSK,
+				  FIELD_PREP(AXI_AD408X_CNTRL_3_PACKET_FORMAT_MSK, val));
+}
+
 static int axi_adc_ad408x_interface_data_align(struct iio_backend *back,
 					       u32 timeout_us)
 {
@@ -660,6 +689,7 @@ static const struct iio_backend_ops adi_ad408x_ops = {
 	.free_buffer = axi_adc_free_buffer,
 	.data_sample_trigger = axi_adc_data_sample_trigger,
 	.filter_type_set = axi_adc_ad408x_filter_type_set,
+	.data_size_set = axi_adc_ad408x_data_size_set,
 	.interface_data_align = axi_adc_ad408x_interface_data_align,
 	.num_lanes_set = axi_adc_num_lanes_set,
 	.debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access),
-- 
2.43.0

[PATCH 2/2] iio: adc: ad4080: configure backend data size

[Antoniu Miclaus]

The AXI backend needs to know the ADC word width in order to pack the
sample data correctly on the bus. During channel setup, program the
backend packet format via iio_backend_data_size_set() using the channel
resolution, so the data is transferred according to the device's
realbits.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 drivers/iio/adc/ad4080.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
index 8d2953341b15..8feb0c7f7fcb 100644
--- a/drivers/iio/adc/ad4080.c
+++ b/drivers/iio/adc/ad4080.c
@@ -698,6 +698,11 @@ static int ad4080_setup_channel(struct ad4080_state *st, unsigned int ch)
 	if (ret)
 		return ret;
 
+	ret = iio_backend_data_size_set(st->back[ch],
+					st->info->channels[0].scan_type.realbits);
+	if (ret)
+		return ret;
+
 	if (!st->lvds_cnv_en)
 		return 0;
 
-- 
2.43.0

Re: [PATCH 2/2] iio: adc: ad4080: configure backend data size

[David Lechner]

On 6/23/26 4:07 AM, Antoniu Miclaus wrote:
> The AXI backend needs to know the ADC word width in order to pack the
> sample data correctly on the bus. During channel setup, program the
> backend packet format via iio_backend_data_size_set() using the channel
> resolution, so the data is transferred according to the device's
> realbits.
> 

Do we need a Fixes: tag?

> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
>  drivers/iio/adc/ad4080.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
> index 8d2953341b15..8feb0c7f7fcb 100644
> --- a/drivers/iio/adc/ad4080.c
> +++ b/drivers/iio/adc/ad4080.c
> @@ -698,6 +698,11 @@ static int ad4080_setup_channel(struct ad4080_state *st, unsigned int ch)
>  	if (ret)
>  		return ret;
>  
> +	ret = iio_backend_data_size_set(st->back[ch],
> +					st->info->channels[0].scan_type.realbits);
> +	if (ret)
> +		return ret;
> +
>  	if (!st->lvds_cnv_en)
>  		return 0;
>  

Re: [PATCH 2/2] iio: adc: ad4080: configure backend data size

[Jonathan Cameron]

On Tue, 23 Jun 2026 18:07:39 -0500
David Lechner <dlechner@baylibre.com> wrote:

> On 6/23/26 4:07 AM, Antoniu Miclaus wrote:
> > The AXI backend needs to know the ADC word width in order to pack the
> > sample data correctly on the bus. During channel setup, program the
> > backend packet format via iio_backend_data_size_set() using the channel
> > resolution, so the data is transferred according to the device's
> > realbits.
> >   
> 
> Do we need a Fixes: tag?
Antoniu?

I'm holding this one for a tag or a reason why not.

Thanks,

Jonathan

> 
> > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> > ---
> >  drivers/iio/adc/ad4080.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
> > index 8d2953341b15..8feb0c7f7fcb 100644
> > --- a/drivers/iio/adc/ad4080.c
> > +++ b/drivers/iio/adc/ad4080.c
> > @@ -698,6 +698,11 @@ static int ad4080_setup_channel(struct ad4080_state *st, unsigned int ch)
> >  	if (ret)
> >  		return ret;
> >  
> > +	ret = iio_backend_data_size_set(st->back[ch],
> > +					st->info->channels[0].scan_type.realbits);
> > +	if (ret)
> > +		return ret;
> > +
> >  	if (!st->lvds_cnv_en)
> >  		return 0;
> >    
> 

RE: [PATCH 2/2] iio: adc: ad4080: configure backend data size

[Miclaus, Antoniu]

Hi David, Jonathan,

> -----Original Message-----
> From: Jonathan Cameron <jic23@kernel.org>
> Sent: Sunday, July 12, 2026 3:49 AM
> To: David Lechner <dlechner@baylibre.com>
> Cc: Miclaus, Antoniu <Antoniu.Miclaus@analog.com>; Sa, Nuno
> <Nuno.Sa@analog.com>; Hennerich, Michael
> <Michael.Hennerich@analog.com>; linux <linux@analog.com>; linux-
> iio@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 2/2] iio: adc: ad4080: configure backend data size
> 
> On Tue, 23 Jun 2026 18:07:39 -0500
> David Lechner <dlechner@baylibre.com> wrote:
> 
> > On 6/23/26 4:07 AM, Antoniu Miclaus wrote:
> > > The AXI backend needs to know the ADC word width in order to pack the
> > > sample data correctly on the bus. During channel setup, program the
> > > backend packet format via iio_backend_data_size_set() using the channel
> > > resolution, so the data is transferred according to the device's
> > > realbits.
> > >
> >
> > Do we need a Fixes: tag?
> Antoniu?
> 
> I'm holding this one for a tag or a reason why not.

Will add the Fixes: tag with some extra explanation in V2 series. Sorry for the delayed response, was a bit out of office.

> Thanks,
> 
> Jonathan
> 
> >
> > > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> > > ---
> > >  drivers/iio/adc/ad4080.c | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c
> > > index 8d2953341b15..8feb0c7f7fcb 100644
> > > --- a/drivers/iio/adc/ad4080.c
> > > +++ b/drivers/iio/adc/ad4080.c
> > > @@ -698,6 +698,11 @@ static int ad4080_setup_channel(struct
> ad4080_state *st, unsigned int ch)
> > >  	if (ret)
> > >  		return ret;
> > >
> > > +	ret = iio_backend_data_size_set(st->back[ch],
> > > +					st->info-
> >channels[0].scan_type.realbits);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > >  	if (!st->lvds_cnv_en)
> > >  		return 0;
> > >
> >

Re: [PATCH 0/2] iio: adc: ad4080: add backend data size configuration

[David Lechner]

On 6/23/26 4:07 AM, Antoniu Miclaus wrote:
> The AD408X AXI core can pack sample data on the bus using different word
> widths (20-bit, 16-bit and 14-bit), selected through the packet format
> field of the CNTRL_3 register. Until now this was left at its default,
> which only matched the AD4080 20-bit resolution.
> 
> This series exposes the packet format through a new data_size_set backend
> operation and has the ad4080 driver program it during channel setup based
> on the channel resolution, so the bus packing always matches the device
> realbits.
> 
> Patch 1 adds the data_size_set operation to the adi-axi-adc backend.
> Patch 2 calls iio_backend_data_size_set() from the ad4080 channel setup.
> 
> Link: https://analogdevicesinc.github.io/hdl/library/axi_ad408x/index.html
> 
> Antoniu Miclaus (2):
>   iio: adc: adi-axi-adc: add data size support for AD408X backend
>   iio: adc: ad4080: configure backend data size
> 
>  drivers/iio/adc/ad4080.c      |  5 +++++
>  drivers/iio/adc/adi-axi-adc.c | 30 ++++++++++++++++++++++++++++++
>  2 files changed, 35 insertions(+)
> 

Reviewed-by: David Lechner <dlechner@baylibre.com>