[PATCH v3 0/6] iio: adc: xilinx-xadc: Add I2C interface support for System Management Wizard

[PATCH v3 0/6] iio: adc: xilinx-xadc: Add I2C interface support for System Management Wizard

[Dileep Kumar Nagavarapu]

The existing driver only supported AXI memory-mapped access to the System
Management Wizard IP. This series extends the driver to support I2C-based
access, which is particularly useful for System Controller usecases.

Key Changes:
- Split the xilinx-xadc-core.c file into two files(xilinx-xadc-core.c and
  xilinx-xadc-platform.c)
- Add required helper functions and callbacks
- Add channel configuration via callback mechanism
- New I2C driver for UltraScale+ System Management Wizard for basic
  voltage and temperature monitoring
- Converted text binding to YAML schema format

Note: We are working on x86 platform support where fixed channel
configuration is used(no DT support). The .setup_channels() function
pointer introduced in patch 2/4 enables different channel configuration
approaches for various platforms.

This series was originally posted by Sai Krishna Potthuri.

Link:https://lore.kernel.org/all/20260323074505.3853353-1-sai.krishna.potthuri@amd.com/

I will be maintaining the series going forward and posting updated
revisions.

Changes in v3:
-> 1/6 - Modernized the driver code with latest kernel coding styles
         and guidelines.
       - Restored one-variable-per-line declarations where no
         functional change  was intended.
       - Added unit suffixes to timing and clock-rate constants.
       - Replaced GENMASK() and FIELD_PREP() in appropriate places.
       - Added guard(spinlock_irq) helper to manage the spinlock
         automatically on scope exit.
       - Added MAINTAINERS entry for XILINX XADC driver.
-> 2/6 - Refactored the xadc_setup_buffer_and_triggers function
         with only two arguments.
       - Added xadc_device_setup() and xadc_device_configure() to handle
         device initialization and configuration separately.
-> 3/6 - Added IIO_XADC namespace to all exported symbols and
         imported the namespace in platform specific modulue.
       - Spliting the driver with modrern driver changes.
-> 4/6 - Added .setup_channels() to handle custom channel setup
         and configuration.
-> 5/6 - Replaced mutex initialization with devm_mutex_init()
       - Removed unused i2c_set_clientdata() usage.
       - Added comments describing the DRP packet layout used
         for I2C  transactions.
       - Added comment for hardware initialization check from xadc i2c
         write and read functions.
       - Wrapped Kconfig help text to conform to kernel style guidelines.
       - Switched device setup error handling to dev_err_probe().
-> 6/6 - Removed write edge default configuration in XADCIF_CFG register.
-> Dropped the binding to YAML conversion patch as this is already sent by
   Pramod Maurya and is in discussion.

Changes in v2:
-> 1/4 - Split the xilinx-xadc-core.c file into two files
         xilinx-xadc-core.c and xilinx-xadc-platform.c(comments from Andy).
-> 2/4 - Referred as .setup_channels instead of setup_channels.
-> 3/4 - Created separate functions for i2c read and write.
       - Created separate file for i2c interface handling.
-> 4/4(comments from Krzysztof)
       - Removed $defs and use it directly under xlnx,channels.
       - Documented the error information in the commit message due to
         vendor prefix properties.
       - Kept only one example as there is not much differences.


Dileep Kumar Nagavarapu (6):
  iio: adc: xilinx-xadc: Modernize driver code
  iio: adc: xilinx-xadc: Add helper functions for the device setup
  iio: adc: xilinx-xadc: Split driver into core and platform files
  iio: adc: xilinx-xadc: Add .setup_channels() to struct xadc_ops
  iio: adc: xilinx-xadc: Add I2C interface support
  iio: adc: xilinx-xadc: Correct Write edge in CFG

 MAINTAINERS                                   |    7 +
 drivers/iio/adc/Kconfig                       |   23 +-
 drivers/iio/adc/Makefile                      |    6 +-
 drivers/iio/adc/xilinx-xadc-core.c            |  886 ++------------
 drivers/iio/adc/xilinx-xadc-events.c          |   54 +-
 drivers/iio/adc/xilinx-xadc-i2c.c             |  228 ++++
 ...inx-xadc-core.c => xilinx-xadc-platform.c} | 1043 ++---------------
 drivers/iio/adc/xilinx-xadc.h                 |  108 +-
 8 files changed, 609 insertions(+), 1746 deletions(-)
 create mode 100644 drivers/iio/adc/xilinx-xadc-i2c.c
 copy drivers/iio/adc/{xilinx-xadc-core.c => xilinx-xadc-platform.c} (34%)

-- 
2.34.1

[PATCH v3 1/6] iio: adc: xilinx-xadc: Modernize driver code

[Dileep Kumar Nagavarapu]

Modernize the XADC driver by updating the code to follow current
kernel development practices.

The changes include:
- Switching to kernel integer types (u16, u32)
- Replacing open-coded bit manipulation with GENMASK(),
  and FIELD_GET() helpers
- Using cleanup and guard helpers where appropriate
- Addressing coding style issues reported by checkpatch.pl
- Removing legacy coding patterns and simplifying the code
- Added MAINTAINERS entry for the Xilinx XADC driver

These updates improve readability, maintainability, and consistency
with modern kernel APIs without changing functionality.

No functional change intended.

Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
---
 MAINTAINERS                          |   7 +
 drivers/iio/adc/xilinx-xadc-core.c   | 351 ++++++++++++---------------
 drivers/iio/adc/xilinx-xadc-events.c |  53 ++--
 drivers/iio/adc/xilinx-xadc.h        |  78 +++---
 4 files changed, 222 insertions(+), 267 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2b1ec46c5919..7868de9c8fac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29647,6 +29647,13 @@ F:	Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
 F:	drivers/watchdog/of_xilinx_wdt.c
 F:	drivers/watchdog/xilinx_wwdt.c
 
+XILINX XADC DRIVER
+M:	Conall O'Griofa <conall.ogriofa@amd.com>
+M:	Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
+L:	linux-iio@vger.kernel.org
+S:	Maintained
+F:	drivers/iio/adc/xilinx-xadc*
+
 XILINX XDMA DRIVER
 M:	Lizhi Hou <lizhi.hou@amd.com>
 M:	Brian Xu <brian.xu@amd.com>
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index cab66bb8cc1c..b468179736f7 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -11,6 +11,9 @@
  *  - AXI XADC interface: Xilinx PG019
  */
 
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
 #include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/err.h>
@@ -34,7 +37,7 @@
 
 #include "xilinx-xadc.h"
 
-static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
+static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT_MS = 500;
 
 /* ZYNQ register definitions */
 #define XADC_ZYNQ_REG_CFG	0x00
@@ -46,28 +49,28 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
 #define XADC_ZYNQ_REG_CTL		0x18
 
 #define XADC_ZYNQ_CFG_ENABLE		BIT(31)
-#define XADC_ZYNQ_CFG_CFIFOTH_MASK	(0xf << 20)
+#define XADC_ZYNQ_CFG_CFIFOTH_MASK	GENMASK(23, 20)
 #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET	20
-#define XADC_ZYNQ_CFG_DFIFOTH_MASK	(0xf << 16)
+#define XADC_ZYNQ_CFG_DFIFOTH_MASK	GENMASK(19, 16)
 #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET	16
 #define XADC_ZYNQ_CFG_WEDGE		BIT(13)
 #define XADC_ZYNQ_CFG_REDGE		BIT(12)
-#define XADC_ZYNQ_CFG_TCKRATE_MASK	(0x3 << 8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV2	(0x0 << 8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV4	(0x1 << 8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV8	(0x2 << 8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV16	(0x3 << 8)
-#define XADC_ZYNQ_CFG_IGAP_MASK		0x1f
+#define XADC_ZYNQ_CFG_TCKRATE_MASK	GENMASK(9, 8)
+#define XADC_ZYNQ_CFG_TCKRATE_DIV2	0
+#define XADC_ZYNQ_CFG_TCKRATE_DIV4	BIT(8)
+#define XADC_ZYNQ_CFG_TCKRATE_DIV8	BIT(9)
+#define XADC_ZYNQ_CFG_TCKRATE_DIV16	GENMASK(9, 8)
+#define XADC_ZYNQ_CFG_IGAP_MASK		GENMASK(4, 0)
 #define XADC_ZYNQ_CFG_IGAP(x)		(x)
 
 #define XADC_ZYNQ_INT_CFIFO_LTH		BIT(9)
 #define XADC_ZYNQ_INT_DFIFO_GTH		BIT(8)
-#define XADC_ZYNQ_INT_ALARM_MASK	0xff
+#define XADC_ZYNQ_INT_ALARM_MASK	GENMASK(7, 0)
 #define XADC_ZYNQ_INT_ALARM_OFFSET	0
 
-#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK	(0xf << 16)
+#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK	GENMASK(19, 16)
 #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET	16
-#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK	(0xf << 12)
+#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK	GENMASK(15, 12)
 #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET	12
 #define XADC_ZYNQ_STATUS_CFIFOF		BIT(11)
 #define XADC_ZYNQ_STATUS_CFIFOE		BIT(10)
@@ -104,7 +107,7 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
 #define XADC_AXI_GIER_ENABLE		BIT(31)
 
 #define XADC_AXI_INT_EOS		BIT(4)
-#define XADC_AXI_INT_ALARM_MASK		0x3c0f
+#define XADC_AXI_INT_ALARM_MASK		(GENMASK(13, 10) | GENMASK(3, 0))
 
 #define XADC_FLAGS_BUFFERED BIT(0)
 #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
@@ -117,16 +120,14 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
  * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
  * but still responsive.
  */
-#define XADC_MAX_SAMPLERATE 150000
+#define XADC_MAX_SAMPLERATE_SPS 150000
 
-static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
-	uint32_t val)
+static void xadc_write_reg(struct xadc *xadc, unsigned int reg, u32 val)
 {
 	writel(val, xadc->base + reg);
 }
 
-static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
-	uint32_t *val)
+static void xadc_read_reg(struct xadc *xadc, unsigned int reg, u32 *val)
 {
 	*val = readl(xadc->base + reg);
 }
@@ -140,60 +141,55 @@ static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
  * sleep and wait for an interrupt that signals that a response is available in
  * the data FIFO.
  */
-
-static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
-	unsigned int n)
+static void xadc_zynq_write_fifo(struct xadc *xadc, u32 *cmd, unsigned int n)
 {
-	unsigned int i;
-
-	for (i = 0; i < n; i++)
+	for (unsigned int i = 0; i < n; i++)
 		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
 }
 
 static void xadc_zynq_drain_fifo(struct xadc *xadc)
 {
-	uint32_t status, tmp;
+	u32 status, tmp;
 
 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
 
+	/*
+	 * Reading XADC_ZYNQ_REG_DFIFO pops one entry from the data FIFO.
+	 * The loop therefore removes one pending entry per iteration and
+	 * terminates once the hardware reports the FIFO empty.
+	 */
 	while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
 		xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
 		xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
 	}
 }
 
-static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
-	unsigned int val)
+static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask, unsigned int val)
 {
-	xadc->zynq_intmask &= ~mask;
-	xadc->zynq_intmask |= val;
+	xadc->zynq_intmask = (xadc->zynq_intmask & ~mask) | (val & mask);
 
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
-		xadc->zynq_intmask | xadc->zynq_masked_alarm);
+	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask | xadc->zynq_masked_alarm);
 }
 
-static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t val)
+static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
 {
-	uint32_t cmd[1];
-	uint32_t tmp;
+	u32 cmd[1];
+	u32 tmp;
 	int ret;
 
-	spin_lock_irq(&xadc->lock);
-	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
-			XADC_ZYNQ_INT_DFIFO_GTH);
+	scoped_guard(spinlock_irq, &xadc->lock) {
+		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
 
-	reinit_completion(&xadc->completion);
+		reinit_completion(&xadc->completion);
 
-	cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
-	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
-	tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
-	tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
+		cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
+		xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
+		xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
+		tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
+		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
 
-	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
-	spin_unlock_irq(&xadc->lock);
+		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
+	}
 
 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
 	if (ret == 0)
@@ -206,49 +202,50 @@ static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
 	return ret;
 }
 
-static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t *val)
+static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
 {
-	uint32_t cmd[2];
-	uint32_t resp, tmp;
+	u32 cmd[2];
+	u32 resp, tmp;
 	int ret;
 
 	cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
 	cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
 
-	spin_lock_irq(&xadc->lock);
-	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
-			XADC_ZYNQ_INT_DFIFO_GTH);
-	xadc_zynq_drain_fifo(xadc);
-	reinit_completion(&xadc->completion);
+	scoped_guard(spinlock_irq, &xadc->lock) {
+		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
+		xadc_zynq_drain_fifo(xadc);
+		reinit_completion(&xadc->completion);
 
-	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
-	tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
-	tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
+		xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
+		xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
+		tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
+		tmp |= FIELD_PREP(XADC_ZYNQ_CFG_DFIFOTH_MASK, 1);
+		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
 
-	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
-	spin_unlock_irq(&xadc->lock);
+		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
+	}
 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
 	if (ret == 0)
 		ret = -EIO;
+
 	if (ret < 0)
 		return ret;
 
 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
 
-	*val = resp & 0xffff;
+	*val = resp;
 
 	return 0;
 }
 
 static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
 {
-	return ((alarm & 0x80) >> 4) |
-		((alarm & 0x78) << 1) |
-		(alarm & 0x07);
+	/*
+	 * Reorder the Zynq PS-XADC alarm bits defined in UG585 to match the common
+	 * XADC driver alarm layout.
+	 */
+	return ((alarm & 0x80) >> 4) | ((alarm & 0x78) << 1) | (alarm & 0x07);
 }
 
 /*
@@ -268,35 +265,32 @@ static void xadc_zynq_unmask_worker(struct work_struct *work)
 
 	misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
 
-	spin_lock_irq(&xadc->lock);
+	scoped_guard(spinlock_irq, &xadc->lock) {
+		/* Clear those bits which are not active anymore */
+		unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
+		xadc->zynq_masked_alarm &= misc_sts;
 
-	/* Clear those bits which are not active anymore */
-	unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
-	xadc->zynq_masked_alarm &= misc_sts;
+		/* Also clear those which are masked out anyway */
+		xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
 
-	/* Also clear those which are masked out anyway */
-	xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
+		/* Clear the interrupts before we unmask them */
+		xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
 
-	/* Clear the interrupts before we unmask them */
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
-
-	xadc_zynq_update_intmsk(xadc, 0, 0);
-
-	spin_unlock_irq(&xadc->lock);
+		xadc_zynq_update_intmsk(xadc, 0, 0);
+	}
 
 	/* if still pending some alarm re-trigger the timer */
 	if (xadc->zynq_masked_alarm) {
 		schedule_delayed_work(&xadc->zynq_unmask_work,
-				msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
+				      msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT_MS));
 	}
-
 }
 
 static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
 {
 	struct iio_dev *indio_dev = devid;
 	struct xadc *xadc = iio_priv(indio_dev);
-	uint32_t status;
+	u32 status;
 
 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
 
@@ -305,13 +299,12 @@ static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
 	if (!status)
 		return IRQ_NONE;
 
-	spin_lock(&xadc->lock);
+	guard(spinlock)(&xadc->lock);
 
 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
 
 	if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
-		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
-			XADC_ZYNQ_INT_DFIFO_GTH);
+		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
 		complete(&xadc->completion);
 	}
 
@@ -324,24 +317,21 @@ static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
 		 */
 		xadc_zynq_update_intmsk(xadc, 0, 0);
 
-		xadc_handle_events(indio_dev,
-				xadc_zynq_transform_alarm(status));
+		xadc_handle_events(indio_dev, xadc_zynq_transform_alarm(status));
 
 		/* unmask the required interrupts in timer. */
 		schedule_delayed_work(&xadc->zynq_unmask_work,
-				msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
+				      msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT_MS));
 	}
-	spin_unlock(&xadc->lock);
 
 	return IRQ_HANDLED;
 }
 
-#define XADC_ZYNQ_TCK_RATE_MAX 50000000
-#define XADC_ZYNQ_IGAP_DEFAULT 20
-#define XADC_ZYNQ_PCAP_RATE_MAX 200000000
+#define XADC_ZYNQ_TCK_RATE_MAX_HZ 50000000
+#define XADC_ZYNQ_IGAP_DEFAULT_CYCLES 20
+#define XADC_ZYNQ_PCAP_RATE_MAX_HZ 200000000
 
-static int xadc_zynq_setup(struct platform_device *pdev,
-	struct iio_dev *indio_dev, int irq)
+static int xadc_zynq_setup(struct platform_device *pdev, struct iio_dev *indio_dev, int irq)
 {
 	struct xadc *xadc = iio_priv(indio_dev);
 	unsigned long pcap_rate;
@@ -352,8 +342,8 @@ static int xadc_zynq_setup(struct platform_device *pdev,
 	int ret;
 
 	/* TODO: Figure out how to make igap and tck_rate configurable */
-	igap = XADC_ZYNQ_IGAP_DEFAULT;
-	tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
+	igap = XADC_ZYNQ_IGAP_DEFAULT_CYCLES;
+	tck_rate = XADC_ZYNQ_TCK_RATE_MAX_HZ;
 
 	xadc->zynq_intmask = ~0;
 
@@ -361,9 +351,8 @@ static int xadc_zynq_setup(struct platform_device *pdev,
 	if (!pcap_rate)
 		return -EINVAL;
 
-	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
-		ret = clk_set_rate(xadc->clk,
-				   (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
+	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX_HZ) {
+		ret = clk_set_rate(xadc->clk, (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX_HZ);
 		if (ret)
 			return ret;
 	}
@@ -372,7 +361,7 @@ static int xadc_zynq_setup(struct platform_device *pdev,
 		div = 2;
 	} else {
 		div = pcap_rate / tck_rate;
-		if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
+		if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX_HZ)
 			div++;
 	}
 
@@ -389,11 +378,10 @@ static int xadc_zynq_setup(struct platform_device *pdev,
 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
-			XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
-			tck_div | XADC_ZYNQ_CFG_IGAP(igap));
+	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE | XADC_ZYNQ_CFG_REDGE |
+			       XADC_ZYNQ_CFG_WEDGE | tck_div | XADC_ZYNQ_CFG_IGAP(igap));
 
-	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
+	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX_HZ) {
 		ret = clk_set_rate(xadc->clk, pcap_rate);
 		if (ret)
 			return ret;
@@ -405,7 +393,7 @@ static int xadc_zynq_setup(struct platform_device *pdev,
 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
 {
 	unsigned int div;
-	uint32_t val;
+	u32 val;
 
 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
 
@@ -429,22 +417,18 @@ static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
 
 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
 {
-	unsigned long flags;
-	uint32_t status;
+	u32 status;
 
 	/* Move OT to bit 7 */
 	alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
 
-	spin_lock_irqsave(&xadc->lock, flags);
+	guard(spinlock_irqsave)(&xadc->lock);
 
 	/* Clear previous interrupts if any. */
 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
 
-	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
-		~alarm & XADC_ZYNQ_INT_ALARM_MASK);
-
-	spin_unlock_irqrestore(&xadc->lock, flags);
+	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK, ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
 }
 
 static const struct xadc_ops xadc_zynq_ops = {
@@ -465,29 +449,24 @@ static const unsigned int xadc_axi_reg_offsets[] = {
 	[XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
 };
 
-static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t *val)
+static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
 {
-	uint32_t val32;
+	u32 val32;
 
-	xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
-		&val32);
-	*val = val32 & 0xffff;
+	xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, &val32);
+	*val = val32;
 
 	return 0;
 }
 
-static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t val)
+static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
 {
-	xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
-		val);
+	xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, val);
 
 	return 0;
 }
 
-static int xadc_axi_setup(struct platform_device *pdev,
-	struct iio_dev *indio_dev, int irq)
+static int xadc_axi_setup(struct platform_device *pdev, struct iio_dev *indio_dev, int irq)
 {
 	struct xadc *xadc = iio_priv(indio_dev);
 
@@ -501,7 +480,7 @@ static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
 {
 	struct iio_dev *indio_dev = devid;
 	struct xadc *xadc = iio_priv(indio_dev);
-	uint32_t status, mask;
+	u32 status, mask;
 	unsigned int events;
 
 	xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
@@ -534,8 +513,7 @@ static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
 
 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
 {
-	uint32_t val;
-	unsigned long flags;
+	u32 val;
 
 	/*
 	 * The order of the bits in the AXI-XADC status register does not match
@@ -543,15 +521,13 @@ static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
 	 * passed the alarm mask in the same order as in the XADC alarm enable
 	 * register.
 	 */
-	alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
-			((alarm & 0xf0) << 6);
+	alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | ((alarm & 0xf0) << 6);
 
-	spin_lock_irqsave(&xadc->lock, flags);
+	guard(spinlock_irqsave)(&xadc->lock);
 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
 	val &= ~XADC_AXI_INT_ALARM_MASK;
 	val |= alarm;
 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
-	spin_unlock_irqrestore(&xadc->lock, flags);
 }
 
 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
@@ -590,10 +566,9 @@ static const struct xadc_ops xadc_us_axi_ops = {
 	.temp_offset = 280231,
 };
 
-static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t mask, uint16_t val)
+static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, u16 mask, u16 val)
 {
-	uint16_t tmp;
+	u16 tmp;
 	int ret;
 
 	ret = _xadc_read_adc_reg(xadc, reg, &tmp);
@@ -603,8 +578,7 @@ static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
 	return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
 }
 
-static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t mask, uint16_t val)
+static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, u16 mask, u16 val)
 {
 	int ret;
 
@@ -620,17 +594,16 @@ static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
 	return xadc->ops->get_dclk_rate(xadc);
 }
 
-static int xadc_update_scan_mode(struct iio_dev *indio_dev,
-	const unsigned long *mask)
+static int xadc_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *mask)
 {
 	struct xadc *xadc = iio_priv(indio_dev);
-	size_t n;
 	void *data;
+	size_t n;
 
 	n = bitmap_weight(mask, iio_get_masklength(indio_dev));
 
-	data = devm_krealloc_array(indio_dev->dev.parent, xadc->data,
-				   n, sizeof(*xadc->data), GFP_KERNEL);
+	data = devm_krealloc_array(indio_dev->dev.parent, xadc->data, n,
+				   sizeof(*xadc->data), GFP_KERNEL);
 	if (!data)
 		return -ENOMEM;
 
@@ -697,7 +670,6 @@ static irqreturn_t xadc_trigger_handler(int irq, void *p)
 static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
 {
 	struct xadc *xadc = iio_trigger_get_drvdata(trigger);
-	unsigned long flags;
 	unsigned int convst;
 	unsigned int val;
 	int ret = 0;
@@ -706,7 +678,7 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
 
 	if (state) {
 		/* Only one of the two triggers can be active at a time. */
-		if (xadc->trigger != NULL) {
+		if (xadc->trigger) {
 			ret = -EBUSY;
 			goto err_out;
 		} else {
@@ -716,23 +688,22 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
 			else
 				convst = 0;
 		}
-		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
-					convst);
+		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC, convst);
 		if (ret)
 			goto err_out;
 	} else {
 		xadc->trigger = NULL;
 	}
 
-	spin_lock_irqsave(&xadc->lock, flags);
-	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
-	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
-	if (state)
-		val |= XADC_AXI_INT_EOS;
-	else
-		val &= ~XADC_AXI_INT_EOS;
-	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
-	spin_unlock_irqrestore(&xadc->lock, flags);
+	scoped_guard(spinlock_irqsave, &xadc->lock) {
+		xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
+		xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
+		if (state)
+			val |= XADC_AXI_INT_EOS;
+		else
+			val &= ~XADC_AXI_INT_EOS;
+		xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
+	}
 
 err_out:
 	mutex_unlock(&xadc->mutex);
@@ -744,8 +715,7 @@ static const struct iio_trigger_ops xadc_trigger_ops = {
 	.set_trigger_state = &xadc_trigger_set_state,
 };
 
-static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
-	const char *name)
+static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev, const char *name)
 {
 	struct device *dev = indio_dev->dev.parent;
 	struct iio_trigger *trig;
@@ -753,7 +723,7 @@ static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
 
 	trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
 				      iio_device_id(indio_dev), name);
-	if (trig == NULL)
+	if (!trig)
 		return ERR_PTR(-ENOMEM);
 
 	trig->ops = &xadc_trigger_ops;
@@ -768,7 +738,7 @@ static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
 
 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
 {
-	uint16_t val;
+	u16 val;
 
 	/*
 	 * As per datasheet the power-down bits are don't care in the
@@ -790,8 +760,7 @@ static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
 		break;
 	}
 
-	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
-		val);
+	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK, val);
 }
 
 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
@@ -805,8 +774,7 @@ static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
 	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
 		return XADC_CONF1_SEQ_SIMULTANEOUS;
 
-	if ((aux_scan_mode & 0xff00) == 0 ||
-		(aux_scan_mode & 0x00ff) == 0)
+	if (!(aux_scan_mode & 0xff00) || !(aux_scan_mode & 0x00ff))
 		return XADC_CONF1_SEQ_CONTINUOUS;
 
 	return XADC_CONF1_SEQ_SIMULTANEOUS;
@@ -839,8 +807,7 @@ static int xadc_postdisable(struct iio_dev *indio_dev)
 	if (ret)
 		return ret;
 
-	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
-				  seq_mode);
+	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, seq_mode);
 	if (ret)
 		return ret;
 
@@ -855,7 +822,7 @@ static int xadc_preenable(struct iio_dev *indio_dev)
 	int ret;
 
 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
-		XADC_CONF1_SEQ_DEFAULT);
+				  XADC_CONF1_SEQ_DEFAULT);
 	if (ret)
 		goto err;
 
@@ -884,8 +851,7 @@ static int xadc_preenable(struct iio_dev *indio_dev)
 	if (ret)
 		goto err;
 
-	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
-		seq_mode);
+	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, seq_mode);
 	if (ret)
 		goto err;
 
@@ -903,14 +869,14 @@ static const struct iio_buffer_setup_ops xadc_buffer_ops = {
 static int xadc_read_samplerate(struct xadc *xadc)
 {
 	unsigned int div;
-	uint16_t val16;
+	u16 val16;
 	int ret;
 
 	ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
 	if (ret)
 		return ret;
 
-	div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
+	div = FIELD_GET(XADC_CONF2_DIV_MASK, val16);
 	if (div < 2)
 		div = 2;
 
@@ -918,11 +884,11 @@ static int xadc_read_samplerate(struct xadc *xadc)
 }
 
 static int xadc_read_raw(struct iio_dev *indio_dev,
-	struct iio_chan_spec const *chan, int *val, int *val2, long info)
+			 struct iio_chan_spec const *chan, int *val, int *val2, long info)
 {
 	struct xadc *xadc = iio_priv(indio_dev);
 	unsigned int bits = chan->scan_type.realbits;
-	uint16_t val16;
+	u16 val16;
 	int ret;
 
 	switch (info) {
@@ -996,8 +962,8 @@ static int xadc_write_samplerate(struct xadc *xadc, int val)
 		return -EINVAL;
 
 	/* Max. 150 kSPS */
-	if (val > XADC_MAX_SAMPLERATE)
-		val = XADC_MAX_SAMPLERATE;
+	if (val > XADC_MAX_SAMPLERATE_SPS)
+		val = XADC_MAX_SAMPLERATE_SPS;
 
 	val *= 26;
 
@@ -1010,7 +976,7 @@ static int xadc_write_samplerate(struct xadc *xadc, int val)
 	 * limit.
 	 */
 	div = clk_rate / val;
-	if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
+	if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE_SPS)
 		div++;
 	if (div < 2)
 		div = 2;
@@ -1018,11 +984,11 @@ static int xadc_write_samplerate(struct xadc *xadc, int val)
 		div = 0xff;
 
 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
-		div << XADC_CONF2_DIV_OFFSET);
+				   div << XADC_CONF2_DIV_OFFSET);
 }
 
 static int xadc_write_raw(struct iio_dev *indio_dev,
-	struct iio_chan_spec const *chan, int val, int val2, long info)
+			  struct iio_chan_spec const *chan, int val, int val2, long info)
 {
 	struct xadc *xadc = iio_priv(indio_dev);
 
@@ -1037,8 +1003,8 @@ static const struct iio_event_spec xadc_temp_events[] = {
 		.type = IIO_EV_TYPE_THRESH,
 		.dir = IIO_EV_DIR_RISING,
 		.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
-				BIT(IIO_EV_INFO_VALUE) |
-				BIT(IIO_EV_INFO_HYSTERESIS),
+				 BIT(IIO_EV_INFO_VALUE) |
+				 BIT(IIO_EV_INFO_HYSTERESIS),
 	},
 };
 
@@ -1294,9 +1260,8 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
 	}
 
 	indio_dev->num_channels = num_channels;
-	indio_dev->channels = devm_krealloc_array(dev, channels,
-						  num_channels, sizeof(*channels),
-						  GFP_KERNEL);
+	indio_dev->channels = devm_krealloc_array(dev, channels, num_channels,
+						  sizeof(*channels), GFP_KERNEL);
 	/* If we can't resize the channels array, just use the original */
 	if (!indio_dev->channels)
 		indio_dev->channels = channels;
@@ -1304,7 +1269,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
 	return 0;
 }
 
-static const char * const xadc_type_names[] = {
+static const char *const xadc_type_names[] = {
 	[XADC_TYPE_S7] = "xadc",
 	[XADC_TYPE_US] = "xilinx-system-monitor",
 };
@@ -1333,8 +1298,7 @@ static int xadc_probe(struct platform_device *pdev)
 		return -EINVAL;
 
 	irq = platform_get_irq_optional(pdev, 0);
-	if (irq < 0 &&
-	    (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
+	if (irq < 0 && (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
 		return irq;
 
 	indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
@@ -1361,10 +1325,8 @@ static int xadc_probe(struct platform_device *pdev)
 		return ret;
 
 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
-		ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
-						      &iio_pollfunc_store_time,
-						      &xadc_trigger_handler,
-						      &xadc_buffer_ops);
+		ret = devm_iio_triggered_buffer_setup(dev, indio_dev, &iio_pollfunc_store_time,
+						      &xadc_trigger_handler, &xadc_buffer_ops);
 		if (ret)
 			return ret;
 
@@ -1373,8 +1335,7 @@ static int xadc_probe(struct platform_device *pdev)
 			if (IS_ERR(xadc->convst_trigger))
 				return PTR_ERR(xadc->convst_trigger);
 
-			xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
-				"samplerate");
+			xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev, "samplerate");
 			if (IS_ERR(xadc->samplerate_trigger))
 				return PTR_ERR(xadc->samplerate_trigger);
 		}
@@ -1393,8 +1354,8 @@ static int xadc_probe(struct platform_device *pdev)
 		if (ret < 0)
 			return ret;
 
-		if (ret > XADC_MAX_SAMPLERATE) {
-			ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
+		if (ret > XADC_MAX_SAMPLERATE_SPS) {
+			ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE_SPS);
 			if (ret < 0)
 				return ret;
 		}
@@ -1417,8 +1378,7 @@ static int xadc_probe(struct platform_device *pdev)
 		return ret;
 
 	for (i = 0; i < 16; i++)
-		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
-			&xadc->threshold[i]);
+		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i), &xadc->threshold[i]);
 
 	ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
 	if (ret)
@@ -1434,8 +1394,7 @@ static int xadc_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
-		bipolar_mask >> 16);
+	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1), bipolar_mask >> 16);
 	if (ret)
 		return ret;
 
diff --git a/drivers/iio/adc/xilinx-xadc-events.c b/drivers/iio/adc/xilinx-xadc-events.c
index c188d3dcab48..e0e1195b7017 100644
--- a/drivers/iio/adc/xilinx-xadc-events.c
+++ b/drivers/iio/adc/xilinx-xadc-events.c
@@ -8,12 +8,11 @@
 
 #include <linux/iio/events.h>
 #include <linux/iio/iio.h>
-#include <linux/kernel.h>
 
 #include "xilinx-xadc.h"
 
-static const struct iio_chan_spec *xadc_event_to_channel(
-	struct iio_dev *indio_dev, unsigned int event)
+static const struct iio_chan_spec *xadc_event_to_channel
+		  (struct iio_dev *indio_dev, unsigned int event)
 {
 	switch (event) {
 	case XADC_THRESHOLD_OT_MAX:
@@ -23,7 +22,7 @@ static const struct iio_chan_spec *xadc_event_to_channel(
 	case XADC_THRESHOLD_VCCAUX_MAX:
 		return &indio_dev->channels[event];
 	default:
-		return &indio_dev->channels[event-1];
+		return &indio_dev->channels[event - 1];
 	}
 }
 
@@ -43,9 +42,10 @@ static void xadc_handle_event(struct iio_dev *indio_dev, unsigned int event)
 		 * events.
 		 */
 		iio_push_event(indio_dev,
-			IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
-				IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
-			iio_get_time_ns(indio_dev));
+			       IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
+						    IIO_EV_TYPE_THRESH,
+						    IIO_EV_DIR_RISING),
+			       iio_get_time_ns(indio_dev));
 	} else {
 		/*
 		 * For other channels we don't know whether it is a upper or
@@ -53,9 +53,10 @@ static void xadc_handle_event(struct iio_dev *indio_dev, unsigned int event)
 		 * channel value if it wants to know.
 		 */
 		iio_push_event(indio_dev,
-			IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
-				IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER),
-			iio_get_time_ns(indio_dev));
+			       IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
+						    IIO_EV_TYPE_THRESH,
+						    IIO_EV_DIR_EITHER),
+			       iio_get_time_ns(indio_dev));
 	}
 }
 
@@ -68,7 +69,7 @@ void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events)
 }
 
 static unsigned int xadc_get_threshold_offset(const struct iio_chan_spec *chan,
-	enum iio_event_direction dir)
+					      enum iio_event_direction dir)
 {
 	unsigned int offset;
 
@@ -110,22 +111,20 @@ static unsigned int xadc_get_alarm_mask(const struct iio_chan_spec *chan)
 	}
 }
 
-int xadc_read_event_config(struct iio_dev *indio_dev,
-	const struct iio_chan_spec *chan, enum iio_event_type type,
-	enum iio_event_direction dir)
+int xadc_read_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
+			   enum iio_event_type type, enum iio_event_direction dir)
 {
 	struct xadc *xadc = iio_priv(indio_dev);
 
 	return (bool)(xadc->alarm_mask & xadc_get_alarm_mask(chan));
 }
 
-int xadc_write_event_config(struct iio_dev *indio_dev,
-	const struct iio_chan_spec *chan, enum iio_event_type type,
-	enum iio_event_direction dir, bool state)
+int xadc_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
+			    enum iio_event_type type, enum iio_event_direction dir, bool state)
 {
 	unsigned int alarm = xadc_get_alarm_mask(chan);
 	struct xadc *xadc = iio_priv(indio_dev);
-	uint16_t cfg, old_cfg;
+	u16 cfg, old_cfg;
 	int ret;
 
 	mutex_lock(&xadc->mutex);
@@ -155,10 +154,9 @@ int xadc_write_event_config(struct iio_dev *indio_dev,
 	return ret;
 }
 
-int xadc_read_event_value(struct iio_dev *indio_dev,
-	const struct iio_chan_spec *chan, enum iio_event_type type,
-	enum iio_event_direction dir, enum iio_event_info info,
-	int *val, int *val2)
+int xadc_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
+			  enum iio_event_type type, enum iio_event_direction dir,
+			  enum iio_event_info info, int *val, int *val2)
 {
 	unsigned int offset = xadc_get_threshold_offset(chan, dir);
 	struct xadc *xadc = iio_priv(indio_dev);
@@ -180,10 +178,9 @@ int xadc_read_event_value(struct iio_dev *indio_dev,
 	return IIO_VAL_INT;
 }
 
-int xadc_write_event_value(struct iio_dev *indio_dev,
-	const struct iio_chan_spec *chan, enum iio_event_type type,
-	enum iio_event_direction dir, enum iio_event_info info,
-	int val, int val2)
+int xadc_write_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
+			   enum iio_event_type type, enum iio_event_direction dir,
+			   enum iio_event_info info, int val, int val2)
 {
 	unsigned int offset = xadc_get_threshold_offset(chan, dir);
 	struct xadc *xadc = iio_priv(indio_dev);
@@ -227,9 +224,9 @@ int xadc_write_event_value(struct iio_dev *indio_dev,
 			xadc->threshold[offset + 4] = 0;
 		else
 			xadc->threshold[offset + 4] = xadc->threshold[offset] -
-					xadc->temp_hysteresis;
+				xadc->temp_hysteresis;
 		ret = _xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(offset + 4),
-			xadc->threshold[offset + 4]);
+					  xadc->threshold[offset + 4]);
 		if (ret)
 			goto out_unlock;
 	}
diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h
index b4d9d4683117..7830135a499f 100644
--- a/drivers/iio/adc/xilinx-xadc.h
+++ b/drivers/iio/adc/xilinx-xadc.h
@@ -19,21 +19,16 @@ struct xadc_ops;
 struct platform_device;
 
 void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events);
-
-int xadc_read_event_config(struct iio_dev *indio_dev,
-	const struct iio_chan_spec *chan, enum iio_event_type type,
-	enum iio_event_direction dir);
-int xadc_write_event_config(struct iio_dev *indio_dev,
-	const struct iio_chan_spec *chan, enum iio_event_type type,
-	enum iio_event_direction dir, bool state);
-int xadc_read_event_value(struct iio_dev *indio_dev,
-	const struct iio_chan_spec *chan, enum iio_event_type type,
-	enum iio_event_direction dir, enum iio_event_info info,
-	int *val, int *val2);
-int xadc_write_event_value(struct iio_dev *indio_dev,
-	const struct iio_chan_spec *chan, enum iio_event_type type,
-	enum iio_event_direction dir, enum iio_event_info info,
-	int val, int val2);
+int xadc_read_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
+			   enum iio_event_type type, enum iio_event_direction dir);
+int xadc_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
+			    enum iio_event_type type, enum iio_event_direction dir, bool state);
+int xadc_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
+			  enum iio_event_type type, enum iio_event_direction dir,
+			  enum iio_event_info info, int *val, int *val2);
+int xadc_write_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
+			   enum iio_event_type type, enum iio_event_direction dir,
+			   enum iio_event_info info, int val, int val2);
 
 enum xadc_external_mux_mode {
 	XADC_EXTERNAL_MUX_NONE,
@@ -47,11 +42,11 @@ struct xadc {
 
 	const struct xadc_ops *ops;
 
-	uint16_t threshold[16];
-	uint16_t temp_hysteresis;
+	u16 threshold[16];
+	u16 temp_hysteresis;
 	unsigned int alarm_mask;
 
-	uint16_t *data;
+	u16 *data;
 
 	struct iio_trigger *trigger;
 	struct iio_trigger *convst_trigger;
@@ -63,7 +58,9 @@ struct xadc {
 	unsigned int zynq_intmask;
 	struct delayed_work zynq_unmask_work;
 
+	/* Serializes register access and device configuration updates */
 	struct mutex mutex;
+	/* Protects interrupt state and FIFO operations */
 	spinlock_t lock;
 
 	struct completion completion;
@@ -75,10 +72,9 @@ enum xadc_type {
 };
 
 struct xadc_ops {
-	int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val);
-	int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val);
-	int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev,
-			int irq);
+	int (*read)(struct xadc *xadc, unsigned int reg, u16 *val);
+	int (*write)(struct xadc *xadc, unsigned int reg, u16 val);
+	int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev, int irq);
 	void (*update_alarm)(struct xadc *xadc, unsigned int alarm);
 	unsigned long (*get_dclk_rate)(struct xadc *xadc);
 	irqreturn_t (*interrupt_handler)(int irq, void *devid);
@@ -89,22 +85,19 @@ struct xadc_ops {
 	int temp_offset;
 };
 
-static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t *val)
+static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
 {
 	lockdep_assert_held(&xadc->mutex);
 	return xadc->ops->read(xadc, reg, val);
 }
 
-static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t val)
+static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
 {
 	lockdep_assert_held(&xadc->mutex);
 	return xadc->ops->write(xadc, reg, val);
 }
 
-static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t *val)
+static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
 {
 	int ret;
 
@@ -114,8 +107,7 @@ static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
 	return ret;
 }
 
-static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
-	uint16_t val)
+static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
 {
 	int ret;
 
@@ -168,22 +160,22 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
 #define XADC_CONF0_MUX			BIT(11)
 #define XADC_CONF0_CHAN(x)		(x)
 
-#define XADC_CONF1_SEQ_MASK		(0xf << 12)
-#define XADC_CONF1_SEQ_DEFAULT		(0 << 12)
-#define XADC_CONF1_SEQ_SINGLE_PASS	(1 << 12)
-#define XADC_CONF1_SEQ_CONTINUOUS	(2 << 12)
-#define XADC_CONF1_SEQ_SINGLE_CHANNEL	(3 << 12)
-#define XADC_CONF1_SEQ_SIMULTANEOUS	(4 << 12)
-#define XADC_CONF1_SEQ_INDEPENDENT	(8 << 12)
-#define XADC_CONF1_ALARM_MASK		0x0f0f
+#define XADC_CONF1_SEQ_MASK		GENMASK(15, 12)
+#define XADC_CONF1_SEQ_DEFAULT		0
+#define XADC_CONF1_SEQ_SINGLE_PASS	BIT(12)
+#define XADC_CONF1_SEQ_CONTINUOUS	BIT(13)
+#define XADC_CONF1_SEQ_SINGLE_CHANNEL	GENMASK(13, 12)
+#define XADC_CONF1_SEQ_SIMULTANEOUS	BIT(14)
+#define XADC_CONF1_SEQ_INDEPENDENT	BIT(15)
+#define XADC_CONF1_ALARM_MASK		(GENMASK(11, 8) | GENMASK(3, 0))
 
-#define XADC_CONF2_DIV_MASK	0xff00
+#define XADC_CONF2_DIV_MASK	GENMASK(15, 8)
 #define XADC_CONF2_DIV_OFFSET	8
 
-#define XADC_CONF2_PD_MASK	(0x3 << 4)
-#define XADC_CONF2_PD_NONE	(0x0 << 4)
-#define XADC_CONF2_PD_ADC_B	(0x2 << 4)
-#define XADC_CONF2_PD_BOTH	(0x3 << 4)
+#define XADC_CONF2_PD_MASK	GENMASK(5, 4)
+#define XADC_CONF2_PD_NONE	0
+#define XADC_CONF2_PD_ADC_B	BIT(5)
+#define XADC_CONF2_PD_BOTH	GENMASK(5, 4)
 
 #define XADC_ALARM_TEMP_MASK		BIT(0)
 #define XADC_ALARM_VCCINT_MASK		BIT(1)
-- 
2.34.1

Re: [PATCH v3 1/6] iio: adc: xilinx-xadc: Modernize driver code

[Pandey, Radhey Shyam]

On 7/29/2026 6:24 PM, Dileep Kumar Nagavarapu wrote:
> Modernize the XADC driver by updating the code to follow current
> kernel development practices.
> 
> The changes include:
> - Switching to kernel integer types (u16, u32)
> - Replacing open-coded bit manipulation with GENMASK(),
>    and FIELD_GET() helpers
> - Using cleanup and guard helpers where appropriate
> - Addressing coding style issues reported by checkpatch.pl
> - Removing legacy coding patterns and simplifying the code
> - Added MAINTAINERS entry for the Xilinx XADC driver
> 
> These updates improve readability, maintainability, and consistency
> with modern kernel APIs without changing functionality.

Too many changes in single patch. Separate each logical change into a
separate patch.

> 
> No functional change intended.
> 
> Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
> ---
>   MAINTAINERS                          |   7 +
>   drivers/iio/adc/xilinx-xadc-core.c   | 351 ++++++++++++---------------
>   drivers/iio/adc/xilinx-xadc-events.c |  53 ++--
>   drivers/iio/adc/xilinx-xadc.h        |  78 +++---
>   4 files changed, 222 insertions(+), 267 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2b1ec46c5919..7868de9c8fac 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -29647,6 +29647,13 @@ F:	Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
>   F:	drivers/watchdog/of_xilinx_wdt.c
>   F:	drivers/watchdog/xilinx_wwdt.c
>   
> +XILINX XADC DRIVER
> +M:	Conall O'Griofa <conall.ogriofa@amd.com>
> +M:	Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> +L:	linux-iio@vger.kernel.org
> +S:	Maintained
> +F:	drivers/iio/adc/xilinx-xadc*
> +
>   XILINX XDMA DRIVER
>   M:	Lizhi Hou <lizhi.hou@amd.com>
>   M:	Brian Xu <brian.xu@amd.com>
> diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
> index cab66bb8cc1c..b468179736f7 100644
> --- a/drivers/iio/adc/xilinx-xadc-core.c
> +++ b/drivers/iio/adc/xilinx-xadc-core.c
> @@ -11,6 +11,9 @@
>    *  - AXI XADC interface: Xilinx PG019
>    */
>   
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/cleanup.h>
>   #include <linux/clk.h>
>   #include <linux/device.h>
>   #include <linux/err.h>
> @@ -34,7 +37,7 @@
>   
>   #include "xilinx-xadc.h"
>   
> -static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
> +static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT_MS = 500;
>   
>   /* ZYNQ register definitions */
>   #define XADC_ZYNQ_REG_CFG	0x00
> @@ -46,28 +49,28 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
>   #define XADC_ZYNQ_REG_CTL		0x18
>   
>   #define XADC_ZYNQ_CFG_ENABLE		BIT(31)
> -#define XADC_ZYNQ_CFG_CFIFOTH_MASK	(0xf << 20)
> +#define XADC_ZYNQ_CFG_CFIFOTH_MASK	GENMASK(23, 20)
>   #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET	20
> -#define XADC_ZYNQ_CFG_DFIFOTH_MASK	(0xf << 16)
> +#define XADC_ZYNQ_CFG_DFIFOTH_MASK	GENMASK(19, 16)
>   #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET	16
>   #define XADC_ZYNQ_CFG_WEDGE		BIT(13)
>   #define XADC_ZYNQ_CFG_REDGE		BIT(12)
> -#define XADC_ZYNQ_CFG_TCKRATE_MASK	(0x3 << 8)
> -#define XADC_ZYNQ_CFG_TCKRATE_DIV2	(0x0 << 8)
> -#define XADC_ZYNQ_CFG_TCKRATE_DIV4	(0x1 << 8)
> -#define XADC_ZYNQ_CFG_TCKRATE_DIV8	(0x2 << 8)
> -#define XADC_ZYNQ_CFG_TCKRATE_DIV16	(0x3 << 8)
> -#define XADC_ZYNQ_CFG_IGAP_MASK		0x1f
> +#define XADC_ZYNQ_CFG_TCKRATE_MASK	GENMASK(9, 8)
> +#define XADC_ZYNQ_CFG_TCKRATE_DIV2	0
> +#define XADC_ZYNQ_CFG_TCKRATE_DIV4	BIT(8)
> +#define XADC_ZYNQ_CFG_TCKRATE_DIV8	BIT(9)
> +#define XADC_ZYNQ_CFG_TCKRATE_DIV16	GENMASK(9, 8)
> +#define XADC_ZYNQ_CFG_IGAP_MASK		GENMASK(4, 0)
>   #define XADC_ZYNQ_CFG_IGAP(x)		(x)
>   
>   #define XADC_ZYNQ_INT_CFIFO_LTH		BIT(9)
>   #define XADC_ZYNQ_INT_DFIFO_GTH		BIT(8)
> -#define XADC_ZYNQ_INT_ALARM_MASK	0xff
> +#define XADC_ZYNQ_INT_ALARM_MASK	GENMASK(7, 0)
>   #define XADC_ZYNQ_INT_ALARM_OFFSET	0
>   
> -#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK	(0xf << 16)
> +#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK	GENMASK(19, 16)
>   #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET	16
> -#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK	(0xf << 12)
> +#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK	GENMASK(15, 12)
>   #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET	12
>   #define XADC_ZYNQ_STATUS_CFIFOF		BIT(11)
>   #define XADC_ZYNQ_STATUS_CFIFOE		BIT(10)
> @@ -104,7 +107,7 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
>   #define XADC_AXI_GIER_ENABLE		BIT(31)
>   
>   #define XADC_AXI_INT_EOS		BIT(4)
> -#define XADC_AXI_INT_ALARM_MASK		0x3c0f
> +#define XADC_AXI_INT_ALARM_MASK		(GENMASK(13, 10) | GENMASK(3, 0))
>   
>   #define XADC_FLAGS_BUFFERED BIT(0)
>   #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
> @@ -117,16 +120,14 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
>    * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
>    * but still responsive.
>    */
> -#define XADC_MAX_SAMPLERATE 150000
> +#define XADC_MAX_SAMPLERATE_SPS 150000
>   
> -static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
> -	uint32_t val)
> +static void xadc_write_reg(struct xadc *xadc, unsigned int reg, u32 val)
>   {
>   	writel(val, xadc->base + reg);
>   }
>   
> -static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
> -	uint32_t *val)
> +static void xadc_read_reg(struct xadc *xadc, unsigned int reg, u32 *val)
>   {
>   	*val = readl(xadc->base + reg);
>   }
> @@ -140,60 +141,55 @@ static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
>    * sleep and wait for an interrupt that signals that a response is available in
>    * the data FIFO.
>    */
> -
> -static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
> -	unsigned int n)
> +static void xadc_zynq_write_fifo(struct xadc *xadc, u32 *cmd, unsigned int n)
>   {
> -	unsigned int i;
> -
> -	for (i = 0; i < n; i++)
> +	for (unsigned int i = 0; i < n; i++)
>   		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
>   }
>   
>   static void xadc_zynq_drain_fifo(struct xadc *xadc)
>   {
> -	uint32_t status, tmp;
> +	u32 status, tmp;
>   
>   	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
>   
> +	/*
> +	 * Reading XADC_ZYNQ_REG_DFIFO pops one entry from the data FIFO.
> +	 * The loop therefore removes one pending entry per iteration and
> +	 * terminates once the hardware reports the FIFO empty.
> +	 */
>   	while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
>   		xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
>   		xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
>   	}
>   }
>   
> -static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
> -	unsigned int val)
> +static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask, unsigned int val)
>   {
> -	xadc->zynq_intmask &= ~mask;
> -	xadc->zynq_intmask |= val;
> +	xadc->zynq_intmask = (xadc->zynq_intmask & ~mask) | (val & mask);
>   
> -	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
> -		xadc->zynq_intmask | xadc->zynq_masked_alarm);
> +	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask | xadc->zynq_masked_alarm);
>   }
>   
> -static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t val)
> +static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
>   {
> -	uint32_t cmd[1];
> -	uint32_t tmp;
> +	u32 cmd[1];
> +	u32 tmp;
>   	int ret;
>   
> -	spin_lock_irq(&xadc->lock);
> -	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
> -			XADC_ZYNQ_INT_DFIFO_GTH);
> +	scoped_guard(spinlock_irq, &xadc->lock) {
> +		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
>   
> -	reinit_completion(&xadc->completion);
> +		reinit_completion(&xadc->completion);
>   
> -	cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
> -	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
> -	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
> -	tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
> -	tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
> -	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
> +		cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
> +		xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
> +		xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
> +		tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
> +		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
>   
> -	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
> -	spin_unlock_irq(&xadc->lock);
> +		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
> +	}
>   
>   	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
>   	if (ret == 0)
> @@ -206,49 +202,50 @@ static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
>   	return ret;
>   }
>   
> -static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t *val)
> +static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
>   {
> -	uint32_t cmd[2];
> -	uint32_t resp, tmp;
> +	u32 cmd[2];
> +	u32 resp, tmp;
>   	int ret;
>   
>   	cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
>   	cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
>   
> -	spin_lock_irq(&xadc->lock);
> -	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
> -			XADC_ZYNQ_INT_DFIFO_GTH);
> -	xadc_zynq_drain_fifo(xadc);
> -	reinit_completion(&xadc->completion);
> +	scoped_guard(spinlock_irq, &xadc->lock) {
> +		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
> +		xadc_zynq_drain_fifo(xadc);
> +		reinit_completion(&xadc->completion);
>   
> -	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
> -	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
> -	tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
> -	tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
> -	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
> +		xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
> +		xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
> +		tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
> +		tmp |= FIELD_PREP(XADC_ZYNQ_CFG_DFIFOTH_MASK, 1);
> +		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
>   
> -	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
> -	spin_unlock_irq(&xadc->lock);
> +		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
> +	}
>   	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
>   	if (ret == 0)
>   		ret = -EIO;
> +
>   	if (ret < 0)
>   		return ret;
>   
>   	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
>   	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
>   
> -	*val = resp & 0xffff;
> +	*val = resp;
>   
>   	return 0;
>   }
>   
>   static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
>   {
> -	return ((alarm & 0x80) >> 4) |
> -		((alarm & 0x78) << 1) |
> -		(alarm & 0x07);
> +	/*
> +	 * Reorder the Zynq PS-XADC alarm bits defined in UG585 to match the common
> +	 * XADC driver alarm layout.
> +	 */
> +	return ((alarm & 0x80) >> 4) | ((alarm & 0x78) << 1) | (alarm & 0x07);
>   }
>   
>   /*
> @@ -268,35 +265,32 @@ static void xadc_zynq_unmask_worker(struct work_struct *work)
>   
>   	misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
>   
> -	spin_lock_irq(&xadc->lock);
> +	scoped_guard(spinlock_irq, &xadc->lock) {
> +		/* Clear those bits which are not active anymore */
> +		unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
> +		xadc->zynq_masked_alarm &= misc_sts;
>   
> -	/* Clear those bits which are not active anymore */
> -	unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
> -	xadc->zynq_masked_alarm &= misc_sts;
> +		/* Also clear those which are masked out anyway */
> +		xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
>   
> -	/* Also clear those which are masked out anyway */
> -	xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
> +		/* Clear the interrupts before we unmask them */
> +		xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
>   
> -	/* Clear the interrupts before we unmask them */
> -	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
> -
> -	xadc_zynq_update_intmsk(xadc, 0, 0);
> -
> -	spin_unlock_irq(&xadc->lock);
> +		xadc_zynq_update_intmsk(xadc, 0, 0);
> +	}
>   
>   	/* if still pending some alarm re-trigger the timer */
>   	if (xadc->zynq_masked_alarm) {
>   		schedule_delayed_work(&xadc->zynq_unmask_work,
> -				msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
> +				      msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT_MS));
>   	}
> -
>   }
>   
>   static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
>   {
>   	struct iio_dev *indio_dev = devid;
>   	struct xadc *xadc = iio_priv(indio_dev);
> -	uint32_t status;
> +	u32 status;
>   
>   	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
>   
> @@ -305,13 +299,12 @@ static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
>   	if (!status)
>   		return IRQ_NONE;
>   
> -	spin_lock(&xadc->lock);
> +	guard(spinlock)(&xadc->lock);
>   
>   	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
>   
>   	if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
> -		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
> -			XADC_ZYNQ_INT_DFIFO_GTH);
> +		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
>   		complete(&xadc->completion);
>   	}
>   
> @@ -324,24 +317,21 @@ static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
>   		 */
>   		xadc_zynq_update_intmsk(xadc, 0, 0);
>   
> -		xadc_handle_events(indio_dev,
> -				xadc_zynq_transform_alarm(status));
> +		xadc_handle_events(indio_dev, xadc_zynq_transform_alarm(status));
>   
>   		/* unmask the required interrupts in timer. */
>   		schedule_delayed_work(&xadc->zynq_unmask_work,
> -				msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
> +				      msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT_MS));
>   	}
> -	spin_unlock(&xadc->lock);
>   
>   	return IRQ_HANDLED;
>   }
>   
> -#define XADC_ZYNQ_TCK_RATE_MAX 50000000
> -#define XADC_ZYNQ_IGAP_DEFAULT 20
> -#define XADC_ZYNQ_PCAP_RATE_MAX 200000000
> +#define XADC_ZYNQ_TCK_RATE_MAX_HZ 50000000
> +#define XADC_ZYNQ_IGAP_DEFAULT_CYCLES 20
> +#define XADC_ZYNQ_PCAP_RATE_MAX_HZ 200000000
>   
> -static int xadc_zynq_setup(struct platform_device *pdev,
> -	struct iio_dev *indio_dev, int irq)
> +static int xadc_zynq_setup(struct platform_device *pdev, struct iio_dev *indio_dev, int irq)
>   {
>   	struct xadc *xadc = iio_priv(indio_dev);
>   	unsigned long pcap_rate;
> @@ -352,8 +342,8 @@ static int xadc_zynq_setup(struct platform_device *pdev,
>   	int ret;
>   
>   	/* TODO: Figure out how to make igap and tck_rate configurable */
> -	igap = XADC_ZYNQ_IGAP_DEFAULT;
> -	tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
> +	igap = XADC_ZYNQ_IGAP_DEFAULT_CYCLES;
> +	tck_rate = XADC_ZYNQ_TCK_RATE_MAX_HZ;
>   
>   	xadc->zynq_intmask = ~0;
>   
> @@ -361,9 +351,8 @@ static int xadc_zynq_setup(struct platform_device *pdev,
>   	if (!pcap_rate)
>   		return -EINVAL;
>   
> -	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
> -		ret = clk_set_rate(xadc->clk,
> -				   (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
> +	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX_HZ) {
> +		ret = clk_set_rate(xadc->clk, (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX_HZ);
>   		if (ret)
>   			return ret;
>   	}
> @@ -372,7 +361,7 @@ static int xadc_zynq_setup(struct platform_device *pdev,
>   		div = 2;
>   	} else {
>   		div = pcap_rate / tck_rate;
> -		if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
> +		if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX_HZ)
>   			div++;
>   	}
>   
> @@ -389,11 +378,10 @@ static int xadc_zynq_setup(struct platform_device *pdev,
>   	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
>   	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
>   	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
> -	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
> -			XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
> -			tck_div | XADC_ZYNQ_CFG_IGAP(igap));
> +	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE | XADC_ZYNQ_CFG_REDGE |
> +			       XADC_ZYNQ_CFG_WEDGE | tck_div | XADC_ZYNQ_CFG_IGAP(igap));
>   
> -	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
> +	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX_HZ) {
>   		ret = clk_set_rate(xadc->clk, pcap_rate);
>   		if (ret)
>   			return ret;
> @@ -405,7 +393,7 @@ static int xadc_zynq_setup(struct platform_device *pdev,
>   static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
>   {
>   	unsigned int div;
> -	uint32_t val;
> +	u32 val;
>   
>   	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
>   
> @@ -429,22 +417,18 @@ static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
>   
>   static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
>   {
> -	unsigned long flags;
> -	uint32_t status;
> +	u32 status;
>   
>   	/* Move OT to bit 7 */
>   	alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
>   
> -	spin_lock_irqsave(&xadc->lock, flags);
> +	guard(spinlock_irqsave)(&xadc->lock);
>   
>   	/* Clear previous interrupts if any. */
>   	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
>   	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
>   
> -	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
> -		~alarm & XADC_ZYNQ_INT_ALARM_MASK);
> -
> -	spin_unlock_irqrestore(&xadc->lock, flags);
> +	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK, ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
>   }
>   
>   static const struct xadc_ops xadc_zynq_ops = {
> @@ -465,29 +449,24 @@ static const unsigned int xadc_axi_reg_offsets[] = {
>   	[XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
>   };
>   
> -static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t *val)
> +static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
>   {
> -	uint32_t val32;
> +	u32 val32;
>   
> -	xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
> -		&val32);
> -	*val = val32 & 0xffff;
> +	xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, &val32);
> +	*val = val32;
>   
>   	return 0;
>   }
>   
> -static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t val)
> +static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
>   {
> -	xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
> -		val);
> +	xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, val);
>   
>   	return 0;
>   }
>   
> -static int xadc_axi_setup(struct platform_device *pdev,
> -	struct iio_dev *indio_dev, int irq)
> +static int xadc_axi_setup(struct platform_device *pdev, struct iio_dev *indio_dev, int irq)
>   {
>   	struct xadc *xadc = iio_priv(indio_dev);
>   
> @@ -501,7 +480,7 @@ static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
>   {
>   	struct iio_dev *indio_dev = devid;
>   	struct xadc *xadc = iio_priv(indio_dev);
> -	uint32_t status, mask;
> +	u32 status, mask;
>   	unsigned int events;
>   
>   	xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
> @@ -534,8 +513,7 @@ static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
>   
>   static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
>   {
> -	uint32_t val;
> -	unsigned long flags;
> +	u32 val;
>   
>   	/*
>   	 * The order of the bits in the AXI-XADC status register does not match
> @@ -543,15 +521,13 @@ static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
>   	 * passed the alarm mask in the same order as in the XADC alarm enable
>   	 * register.
>   	 */
> -	alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
> -			((alarm & 0xf0) << 6);
> +	alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | ((alarm & 0xf0) << 6);
>   
> -	spin_lock_irqsave(&xadc->lock, flags);
> +	guard(spinlock_irqsave)(&xadc->lock);
>   	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
>   	val &= ~XADC_AXI_INT_ALARM_MASK;
>   	val |= alarm;
>   	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
> -	spin_unlock_irqrestore(&xadc->lock, flags);
>   }
>   
>   static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
> @@ -590,10 +566,9 @@ static const struct xadc_ops xadc_us_axi_ops = {
>   	.temp_offset = 280231,
>   };
>   
> -static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t mask, uint16_t val)
> +static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, u16 mask, u16 val)
>   {
> -	uint16_t tmp;
> +	u16 tmp;
>   	int ret;
>   
>   	ret = _xadc_read_adc_reg(xadc, reg, &tmp);
> @@ -603,8 +578,7 @@ static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
>   	return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
>   }
>   
> -static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t mask, uint16_t val)
> +static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, u16 mask, u16 val)
>   {
>   	int ret;
>   
> @@ -620,17 +594,16 @@ static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
>   	return xadc->ops->get_dclk_rate(xadc);
>   }
>   
> -static int xadc_update_scan_mode(struct iio_dev *indio_dev,
> -	const unsigned long *mask)
> +static int xadc_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *mask)
>   {
>   	struct xadc *xadc = iio_priv(indio_dev);
> -	size_t n;
>   	void *data;
> +	size_t n;
>   
>   	n = bitmap_weight(mask, iio_get_masklength(indio_dev));
>   
> -	data = devm_krealloc_array(indio_dev->dev.parent, xadc->data,
> -				   n, sizeof(*xadc->data), GFP_KERNEL);
> +	data = devm_krealloc_array(indio_dev->dev.parent, xadc->data, n,
> +				   sizeof(*xadc->data), GFP_KERNEL);
>   	if (!data)
>   		return -ENOMEM;
>   
> @@ -697,7 +670,6 @@ static irqreturn_t xadc_trigger_handler(int irq, void *p)
>   static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
>   {
>   	struct xadc *xadc = iio_trigger_get_drvdata(trigger);
> -	unsigned long flags;
>   	unsigned int convst;
>   	unsigned int val;
>   	int ret = 0;
> @@ -706,7 +678,7 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
>   
>   	if (state) {
>   		/* Only one of the two triggers can be active at a time. */
> -		if (xadc->trigger != NULL) {
> +		if (xadc->trigger) {
>   			ret = -EBUSY;
>   			goto err_out;
>   		} else {
> @@ -716,23 +688,22 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
>   			else
>   				convst = 0;
>   		}
> -		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
> -					convst);
> +		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC, convst);
>   		if (ret)
>   			goto err_out;
>   	} else {
>   		xadc->trigger = NULL;
>   	}
>   
> -	spin_lock_irqsave(&xadc->lock, flags);
> -	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
> -	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
> -	if (state)
> -		val |= XADC_AXI_INT_EOS;
> -	else
> -		val &= ~XADC_AXI_INT_EOS;
> -	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
> -	spin_unlock_irqrestore(&xadc->lock, flags);
> +	scoped_guard(spinlock_irqsave, &xadc->lock) {
> +		xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
> +		xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
> +		if (state)
> +			val |= XADC_AXI_INT_EOS;
> +		else
> +			val &= ~XADC_AXI_INT_EOS;
> +		xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
> +	}
>   
>   err_out:
>   	mutex_unlock(&xadc->mutex);
> @@ -744,8 +715,7 @@ static const struct iio_trigger_ops xadc_trigger_ops = {
>   	.set_trigger_state = &xadc_trigger_set_state,
>   };
>   
> -static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
> -	const char *name)
> +static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev, const char *name)
>   {
>   	struct device *dev = indio_dev->dev.parent;
>   	struct iio_trigger *trig;
> @@ -753,7 +723,7 @@ static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
>   
>   	trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
>   				      iio_device_id(indio_dev), name);
> -	if (trig == NULL)
> +	if (!trig)
>   		return ERR_PTR(-ENOMEM);
>   
>   	trig->ops = &xadc_trigger_ops;
> @@ -768,7 +738,7 @@ static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
>   
>   static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
>   {
> -	uint16_t val;
> +	u16 val;
>   
>   	/*
>   	 * As per datasheet the power-down bits are don't care in the
> @@ -790,8 +760,7 @@ static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
>   		break;
>   	}
>   
> -	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
> -		val);
> +	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK, val);
>   }
>   
>   static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
> @@ -805,8 +774,7 @@ static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
>   	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
>   		return XADC_CONF1_SEQ_SIMULTANEOUS;
>   
> -	if ((aux_scan_mode & 0xff00) == 0 ||
> -		(aux_scan_mode & 0x00ff) == 0)
> +	if (!(aux_scan_mode & 0xff00) || !(aux_scan_mode & 0x00ff))
>   		return XADC_CONF1_SEQ_CONTINUOUS;
>   
>   	return XADC_CONF1_SEQ_SIMULTANEOUS;
> @@ -839,8 +807,7 @@ static int xadc_postdisable(struct iio_dev *indio_dev)
>   	if (ret)
>   		return ret;
>   
> -	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
> -				  seq_mode);
> +	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, seq_mode);
>   	if (ret)
>   		return ret;
>   
> @@ -855,7 +822,7 @@ static int xadc_preenable(struct iio_dev *indio_dev)
>   	int ret;
>   
>   	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
> -		XADC_CONF1_SEQ_DEFAULT);
> +				  XADC_CONF1_SEQ_DEFAULT);
>   	if (ret)
>   		goto err;
>   
> @@ -884,8 +851,7 @@ static int xadc_preenable(struct iio_dev *indio_dev)
>   	if (ret)
>   		goto err;
>   
> -	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
> -		seq_mode);
> +	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, seq_mode);
>   	if (ret)
>   		goto err;
>   
> @@ -903,14 +869,14 @@ static const struct iio_buffer_setup_ops xadc_buffer_ops = {
>   static int xadc_read_samplerate(struct xadc *xadc)
>   {
>   	unsigned int div;
> -	uint16_t val16;
> +	u16 val16;
>   	int ret;
>   
>   	ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
>   	if (ret)
>   		return ret;
>   
> -	div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
> +	div = FIELD_GET(XADC_CONF2_DIV_MASK, val16);
>   	if (div < 2)
>   		div = 2;
>   
> @@ -918,11 +884,11 @@ static int xadc_read_samplerate(struct xadc *xadc)
>   }
>   
>   static int xadc_read_raw(struct iio_dev *indio_dev,
> -	struct iio_chan_spec const *chan, int *val, int *val2, long info)
> +			 struct iio_chan_spec const *chan, int *val, int *val2, long info)
>   {
>   	struct xadc *xadc = iio_priv(indio_dev);
>   	unsigned int bits = chan->scan_type.realbits;
> -	uint16_t val16;
> +	u16 val16;
>   	int ret;
>   
>   	switch (info) {
> @@ -996,8 +962,8 @@ static int xadc_write_samplerate(struct xadc *xadc, int val)
>   		return -EINVAL;
>   
>   	/* Max. 150 kSPS */
> -	if (val > XADC_MAX_SAMPLERATE)
> -		val = XADC_MAX_SAMPLERATE;
> +	if (val > XADC_MAX_SAMPLERATE_SPS)
> +		val = XADC_MAX_SAMPLERATE_SPS;
>   
>   	val *= 26;
>   
> @@ -1010,7 +976,7 @@ static int xadc_write_samplerate(struct xadc *xadc, int val)
>   	 * limit.
>   	 */
>   	div = clk_rate / val;
> -	if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
> +	if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE_SPS)
>   		div++;
>   	if (div < 2)
>   		div = 2;
> @@ -1018,11 +984,11 @@ static int xadc_write_samplerate(struct xadc *xadc, int val)
>   		div = 0xff;
>   
>   	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
> -		div << XADC_CONF2_DIV_OFFSET);
> +				   div << XADC_CONF2_DIV_OFFSET);
>   }
>   
>   static int xadc_write_raw(struct iio_dev *indio_dev,
> -	struct iio_chan_spec const *chan, int val, int val2, long info)
> +			  struct iio_chan_spec const *chan, int val, int val2, long info)
>   {
>   	struct xadc *xadc = iio_priv(indio_dev);
>   
> @@ -1037,8 +1003,8 @@ static const struct iio_event_spec xadc_temp_events[] = {
>   		.type = IIO_EV_TYPE_THRESH,
>   		.dir = IIO_EV_DIR_RISING,
>   		.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
> -				BIT(IIO_EV_INFO_VALUE) |
> -				BIT(IIO_EV_INFO_HYSTERESIS),
> +				 BIT(IIO_EV_INFO_VALUE) |
> +				 BIT(IIO_EV_INFO_HYSTERESIS),
>   	},
>   };
>   
> @@ -1294,9 +1260,8 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
>   	}
>   
>   	indio_dev->num_channels = num_channels;
> -	indio_dev->channels = devm_krealloc_array(dev, channels,
> -						  num_channels, sizeof(*channels),
> -						  GFP_KERNEL);
> +	indio_dev->channels = devm_krealloc_array(dev, channels, num_channels,
> +						  sizeof(*channels), GFP_KERNEL);
>   	/* If we can't resize the channels array, just use the original */
>   	if (!indio_dev->channels)
>   		indio_dev->channels = channels;
> @@ -1304,7 +1269,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
>   	return 0;
>   }
>   
> -static const char * const xadc_type_names[] = {
> +static const char *const xadc_type_names[] = {
>   	[XADC_TYPE_S7] = "xadc",
>   	[XADC_TYPE_US] = "xilinx-system-monitor",
>   };
> @@ -1333,8 +1298,7 @@ static int xadc_probe(struct platform_device *pdev)
>   		return -EINVAL;
>   
>   	irq = platform_get_irq_optional(pdev, 0);
> -	if (irq < 0 &&
> -	    (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
> +	if (irq < 0 && (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
>   		return irq;
>   
>   	indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
> @@ -1361,10 +1325,8 @@ static int xadc_probe(struct platform_device *pdev)
>   		return ret;
>   
>   	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
> -		ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
> -						      &iio_pollfunc_store_time,
> -						      &xadc_trigger_handler,
> -						      &xadc_buffer_ops);
> +		ret = devm_iio_triggered_buffer_setup(dev, indio_dev, &iio_pollfunc_store_time,
> +						      &xadc_trigger_handler, &xadc_buffer_ops);
>   		if (ret)
>   			return ret;
>   
> @@ -1373,8 +1335,7 @@ static int xadc_probe(struct platform_device *pdev)
>   			if (IS_ERR(xadc->convst_trigger))
>   				return PTR_ERR(xadc->convst_trigger);
>   
> -			xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
> -				"samplerate");
> +			xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev, "samplerate");
>   			if (IS_ERR(xadc->samplerate_trigger))
>   				return PTR_ERR(xadc->samplerate_trigger);
>   		}
> @@ -1393,8 +1354,8 @@ static int xadc_probe(struct platform_device *pdev)
>   		if (ret < 0)
>   			return ret;
>   
> -		if (ret > XADC_MAX_SAMPLERATE) {
> -			ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
> +		if (ret > XADC_MAX_SAMPLERATE_SPS) {
> +			ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE_SPS);
>   			if (ret < 0)
>   				return ret;
>   		}
> @@ -1417,8 +1378,7 @@ static int xadc_probe(struct platform_device *pdev)
>   		return ret;
>   
>   	for (i = 0; i < 16; i++)
> -		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
> -			&xadc->threshold[i]);
> +		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i), &xadc->threshold[i]);
>   
>   	ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
>   	if (ret)
> @@ -1434,8 +1394,7 @@ static int xadc_probe(struct platform_device *pdev)
>   	if (ret)
>   		return ret;
>   
> -	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
> -		bipolar_mask >> 16);
> +	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1), bipolar_mask >> 16);
>   	if (ret)
>   		return ret;
>   
> diff --git a/drivers/iio/adc/xilinx-xadc-events.c b/drivers/iio/adc/xilinx-xadc-events.c
> index c188d3dcab48..e0e1195b7017 100644
> --- a/drivers/iio/adc/xilinx-xadc-events.c
> +++ b/drivers/iio/adc/xilinx-xadc-events.c
> @@ -8,12 +8,11 @@
>   
>   #include <linux/iio/events.h>
>   #include <linux/iio/iio.h>
> -#include <linux/kernel.h>
>   
>   #include "xilinx-xadc.h"
>   
> -static const struct iio_chan_spec *xadc_event_to_channel(
> -	struct iio_dev *indio_dev, unsigned int event)
> +static const struct iio_chan_spec *xadc_event_to_channel
> +		  (struct iio_dev *indio_dev, unsigned int event)
>   {
>   	switch (event) {
>   	case XADC_THRESHOLD_OT_MAX:
> @@ -23,7 +22,7 @@ static const struct iio_chan_spec *xadc_event_to_channel(
>   	case XADC_THRESHOLD_VCCAUX_MAX:
>   		return &indio_dev->channels[event];
>   	default:
> -		return &indio_dev->channels[event-1];
> +		return &indio_dev->channels[event - 1];
>   	}
>   }
>   
> @@ -43,9 +42,10 @@ static void xadc_handle_event(struct iio_dev *indio_dev, unsigned int event)
>   		 * events.
>   		 */
>   		iio_push_event(indio_dev,
> -			IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
> -				IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
> -			iio_get_time_ns(indio_dev));
> +			       IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
> +						    IIO_EV_TYPE_THRESH,
> +						    IIO_EV_DIR_RISING),
> +			       iio_get_time_ns(indio_dev));
>   	} else {
>   		/*
>   		 * For other channels we don't know whether it is a upper or
> @@ -53,9 +53,10 @@ static void xadc_handle_event(struct iio_dev *indio_dev, unsigned int event)
>   		 * channel value if it wants to know.
>   		 */
>   		iio_push_event(indio_dev,
> -			IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
> -				IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER),
> -			iio_get_time_ns(indio_dev));
> +			       IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
> +						    IIO_EV_TYPE_THRESH,
> +						    IIO_EV_DIR_EITHER),
> +			       iio_get_time_ns(indio_dev));
>   	}
>   }
>   
> @@ -68,7 +69,7 @@ void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events)
>   }
>   
>   static unsigned int xadc_get_threshold_offset(const struct iio_chan_spec *chan,
> -	enum iio_event_direction dir)
> +					      enum iio_event_direction dir)
>   {
>   	unsigned int offset;
>   
> @@ -110,22 +111,20 @@ static unsigned int xadc_get_alarm_mask(const struct iio_chan_spec *chan)
>   	}
>   }
>   
> -int xadc_read_event_config(struct iio_dev *indio_dev,
> -	const struct iio_chan_spec *chan, enum iio_event_type type,
> -	enum iio_event_direction dir)
> +int xadc_read_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
> +			   enum iio_event_type type, enum iio_event_direction dir)
>   {
>   	struct xadc *xadc = iio_priv(indio_dev);
>   
>   	return (bool)(xadc->alarm_mask & xadc_get_alarm_mask(chan));
>   }
>   
> -int xadc_write_event_config(struct iio_dev *indio_dev,
> -	const struct iio_chan_spec *chan, enum iio_event_type type,
> -	enum iio_event_direction dir, bool state)
> +int xadc_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
> +			    enum iio_event_type type, enum iio_event_direction dir, bool state)
>   {
>   	unsigned int alarm = xadc_get_alarm_mask(chan);
>   	struct xadc *xadc = iio_priv(indio_dev);
> -	uint16_t cfg, old_cfg;
> +	u16 cfg, old_cfg;
>   	int ret;
>   
>   	mutex_lock(&xadc->mutex);
> @@ -155,10 +154,9 @@ int xadc_write_event_config(struct iio_dev *indio_dev,
>   	return ret;
>   }
>   
> -int xadc_read_event_value(struct iio_dev *indio_dev,
> -	const struct iio_chan_spec *chan, enum iio_event_type type,
> -	enum iio_event_direction dir, enum iio_event_info info,
> -	int *val, int *val2)
> +int xadc_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
> +			  enum iio_event_type type, enum iio_event_direction dir,
> +			  enum iio_event_info info, int *val, int *val2)
>   {
>   	unsigned int offset = xadc_get_threshold_offset(chan, dir);
>   	struct xadc *xadc = iio_priv(indio_dev);
> @@ -180,10 +178,9 @@ int xadc_read_event_value(struct iio_dev *indio_dev,
>   	return IIO_VAL_INT;
>   }
>   
> -int xadc_write_event_value(struct iio_dev *indio_dev,
> -	const struct iio_chan_spec *chan, enum iio_event_type type,
> -	enum iio_event_direction dir, enum iio_event_info info,
> -	int val, int val2)
> +int xadc_write_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
> +			   enum iio_event_type type, enum iio_event_direction dir,
> +			   enum iio_event_info info, int val, int val2)
>   {
>   	unsigned int offset = xadc_get_threshold_offset(chan, dir);
>   	struct xadc *xadc = iio_priv(indio_dev);
> @@ -227,9 +224,9 @@ int xadc_write_event_value(struct iio_dev *indio_dev,
>   			xadc->threshold[offset + 4] = 0;
>   		else
>   			xadc->threshold[offset + 4] = xadc->threshold[offset] -
> -					xadc->temp_hysteresis;
> +				xadc->temp_hysteresis;
>   		ret = _xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(offset + 4),
> -			xadc->threshold[offset + 4]);
> +					  xadc->threshold[offset + 4]);
>   		if (ret)
>   			goto out_unlock;
>   	}
> diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h
> index b4d9d4683117..7830135a499f 100644
> --- a/drivers/iio/adc/xilinx-xadc.h
> +++ b/drivers/iio/adc/xilinx-xadc.h
> @@ -19,21 +19,16 @@ struct xadc_ops;
>   struct platform_device;
>   
>   void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events);
> -
> -int xadc_read_event_config(struct iio_dev *indio_dev,
> -	const struct iio_chan_spec *chan, enum iio_event_type type,
> -	enum iio_event_direction dir);
> -int xadc_write_event_config(struct iio_dev *indio_dev,
> -	const struct iio_chan_spec *chan, enum iio_event_type type,
> -	enum iio_event_direction dir, bool state);
> -int xadc_read_event_value(struct iio_dev *indio_dev,
> -	const struct iio_chan_spec *chan, enum iio_event_type type,
> -	enum iio_event_direction dir, enum iio_event_info info,
> -	int *val, int *val2);
> -int xadc_write_event_value(struct iio_dev *indio_dev,
> -	const struct iio_chan_spec *chan, enum iio_event_type type,
> -	enum iio_event_direction dir, enum iio_event_info info,
> -	int val, int val2);
> +int xadc_read_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
> +			   enum iio_event_type type, enum iio_event_direction dir);
> +int xadc_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
> +			    enum iio_event_type type, enum iio_event_direction dir, bool state);
> +int xadc_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
> +			  enum iio_event_type type, enum iio_event_direction dir,
> +			  enum iio_event_info info, int *val, int *val2);
> +int xadc_write_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
> +			   enum iio_event_type type, enum iio_event_direction dir,
> +			   enum iio_event_info info, int val, int val2);
>   
>   enum xadc_external_mux_mode {
>   	XADC_EXTERNAL_MUX_NONE,
> @@ -47,11 +42,11 @@ struct xadc {
>   
>   	const struct xadc_ops *ops;
>   
> -	uint16_t threshold[16];
> -	uint16_t temp_hysteresis;
> +	u16 threshold[16];
> +	u16 temp_hysteresis;
>   	unsigned int alarm_mask;
>   
> -	uint16_t *data;
> +	u16 *data;
>   
>   	struct iio_trigger *trigger;
>   	struct iio_trigger *convst_trigger;
> @@ -63,7 +58,9 @@ struct xadc {
>   	unsigned int zynq_intmask;
>   	struct delayed_work zynq_unmask_work;
>   
> +	/* Serializes register access and device configuration updates */
>   	struct mutex mutex;
> +	/* Protects interrupt state and FIFO operations */
>   	spinlock_t lock;
>   
>   	struct completion completion;
> @@ -75,10 +72,9 @@ enum xadc_type {
>   };
>   
>   struct xadc_ops {
> -	int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val);
> -	int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val);
> -	int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev,
> -			int irq);
> +	int (*read)(struct xadc *xadc, unsigned int reg, u16 *val);
> +	int (*write)(struct xadc *xadc, unsigned int reg, u16 val);
> +	int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev, int irq);
>   	void (*update_alarm)(struct xadc *xadc, unsigned int alarm);
>   	unsigned long (*get_dclk_rate)(struct xadc *xadc);
>   	irqreturn_t (*interrupt_handler)(int irq, void *devid);
> @@ -89,22 +85,19 @@ struct xadc_ops {
>   	int temp_offset;
>   };
>   
> -static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t *val)
> +static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
>   {
>   	lockdep_assert_held(&xadc->mutex);
>   	return xadc->ops->read(xadc, reg, val);
>   }
>   
> -static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t val)
> +static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
>   {
>   	lockdep_assert_held(&xadc->mutex);
>   	return xadc->ops->write(xadc, reg, val);
>   }
>   
> -static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t *val)
> +static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
>   {
>   	int ret;
>   
> @@ -114,8 +107,7 @@ static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
>   	return ret;
>   }
>   
> -static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
> -	uint16_t val)
> +static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
>   {
>   	int ret;
>   
> @@ -168,22 +160,22 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
>   #define XADC_CONF0_MUX			BIT(11)
>   #define XADC_CONF0_CHAN(x)		(x)
>   
> -#define XADC_CONF1_SEQ_MASK		(0xf << 12)
> -#define XADC_CONF1_SEQ_DEFAULT		(0 << 12)
> -#define XADC_CONF1_SEQ_SINGLE_PASS	(1 << 12)
> -#define XADC_CONF1_SEQ_CONTINUOUS	(2 << 12)
> -#define XADC_CONF1_SEQ_SINGLE_CHANNEL	(3 << 12)
> -#define XADC_CONF1_SEQ_SIMULTANEOUS	(4 << 12)
> -#define XADC_CONF1_SEQ_INDEPENDENT	(8 << 12)
> -#define XADC_CONF1_ALARM_MASK		0x0f0f
> +#define XADC_CONF1_SEQ_MASK		GENMASK(15, 12)
> +#define XADC_CONF1_SEQ_DEFAULT		0
> +#define XADC_CONF1_SEQ_SINGLE_PASS	BIT(12)
> +#define XADC_CONF1_SEQ_CONTINUOUS	BIT(13)
> +#define XADC_CONF1_SEQ_SINGLE_CHANNEL	GENMASK(13, 12)
> +#define XADC_CONF1_SEQ_SIMULTANEOUS	BIT(14)
> +#define XADC_CONF1_SEQ_INDEPENDENT	BIT(15)
> +#define XADC_CONF1_ALARM_MASK		(GENMASK(11, 8) | GENMASK(3, 0))
>   
> -#define XADC_CONF2_DIV_MASK	0xff00
> +#define XADC_CONF2_DIV_MASK	GENMASK(15, 8)
>   #define XADC_CONF2_DIV_OFFSET	8
>   
> -#define XADC_CONF2_PD_MASK	(0x3 << 4)
> -#define XADC_CONF2_PD_NONE	(0x0 << 4)
> -#define XADC_CONF2_PD_ADC_B	(0x2 << 4)
> -#define XADC_CONF2_PD_BOTH	(0x3 << 4)
> +#define XADC_CONF2_PD_MASK	GENMASK(5, 4)
> +#define XADC_CONF2_PD_NONE	0
> +#define XADC_CONF2_PD_ADC_B	BIT(5)
> +#define XADC_CONF2_PD_BOTH	GENMASK(5, 4)
>   
>   #define XADC_ALARM_TEMP_MASK		BIT(0)
>   #define XADC_ALARM_VCCINT_MASK		BIT(1)

Re: [PATCH v3 1/6] iio: adc: xilinx-xadc: Modernize driver code

[Joshua Crofts]

On Wed, 29 Jul 2026 18:24:50 +0530
Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com> wrote:

> Modernize the XADC driver by updating the code to follow current
> kernel development practices.
> 
> The changes include:
> - Switching to kernel integer types (u16, u32)
> - Replacing open-coded bit manipulation with GENMASK(),
>   and FIELD_GET() helpers
> - Using cleanup and guard helpers where appropriate
> - Addressing coding style issues reported by checkpatch.pl
> - Removing legacy coding patterns and simplifying the code
> - Added MAINTAINERS entry for the Xilinx XADC driver
> 
> These updates improve readability, maintainability, and consistency
> with modern kernel APIs without changing functionality.
> 
> No functional change intended.
> 
> Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
> ---

I thought I was reading a cover letter and then I realized that these
are all changes in one patch only. Please separate this into multiple
patches, I count 6 separate patches.

>  MAINTAINERS                          |   7 +
>  drivers/iio/adc/xilinx-xadc-core.c   | 351 ++++++++++++---------------
>  drivers/iio/adc/xilinx-xadc-events.c |  53 ++--
>  drivers/iio/adc/xilinx-xadc.h        |  78 +++---
>  4 files changed, 222 insertions(+), 267 deletions(-)
> 

...

> diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
> index cab66bb8cc1c..b468179736f7 100644
> --- a/drivers/iio/adc/xilinx-xadc-core.c
> +++ b/drivers/iio/adc/xilinx-xadc-core.c
> @@ -11,6 +11,9 @@
>   *  - AXI XADC interface: Xilinx PG019
>   */
>  
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/cleanup.h>

Since you're moving the driver to kernel types, include <linux/types.h>
as well.

Maybe you could do an additional patch that removes the catch-all kernel.h
header and adds used/removes unused headers in accordance with the IWYU
principle?

-- 
Kind regards,
Joshua Crofts

[PATCH v3 2/6] iio: adc: xilinx-xadc: Add helper functions for the device setup

[Dileep Kumar Nagavarapu]

Refactor the platform driver probe function by extracting device
setup and configuration logic into reusable helper functions:
xadc_device_setup(): handles IIO device allocation and basic setup
xadc_device_configure(): handles device tree parsing and bipolar mask
configuration

This refactoring reduces code duplication and prepares for sharing the
common setup logic between platform and I2C drivers.

Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
---
 drivers/iio/adc/xilinx-xadc-core.c | 104 ++++++++++++++++++++---------
 1 file changed, 73 insertions(+), 31 deletions(-)

diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index b468179736f7..dd1470d2bf9b 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -194,12 +194,13 @@ static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
 	if (ret == 0)
 		ret = -EIO;
-	else
-		ret = 0;
+
+	if (ret < 0)
+		return ret;
 
 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
 
-	return ret;
+	return 0;
 }
 
 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
@@ -950,6 +951,33 @@ static int xadc_read_raw(struct iio_dev *indio_dev,
 	}
 }
 
+int xadc_setup_buffer_and_triggers(struct iio_dev *indio_dev, int irq)
+{
+	struct xadc *xadc = iio_priv(indio_dev);
+	struct device *dev = indio_dev->dev.parent;
+	int ret;
+
+	if (!(xadc->ops->flags & XADC_FLAGS_BUFFERED))
+		return 0;
+
+	ret = devm_iio_triggered_buffer_setup(dev, indio_dev, &iio_pollfunc_store_time,
+					      &xadc_trigger_handler, &xadc_buffer_ops);
+	if (ret)
+		return ret;
+
+	if (irq > 0) {
+		xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
+		if (IS_ERR(xadc->convst_trigger))
+			return PTR_ERR(xadc->convst_trigger);
+
+		xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev, "samplerate");
+		if (IS_ERR(xadc->samplerate_trigger))
+			return PTR_ERR(xadc->samplerate_trigger);
+	}
+
+	return 0;
+}
+
 static int xadc_write_samplerate(struct xadc *xadc, int val)
 {
 	unsigned long clk_rate = xadc_get_dclk_rate(xadc);
@@ -1274,6 +1302,41 @@ static const char *const xadc_type_names[] = {
 	[XADC_TYPE_US] = "xilinx-system-monitor",
 };
 
+struct iio_dev *xadc_device_setup(struct device *dev, int size, const struct xadc_ops **ops)
+{
+	struct iio_dev *indio_dev;
+
+	*ops = device_get_match_data(dev);
+
+	indio_dev = devm_iio_device_alloc(dev, size);
+	if (!indio_dev)
+		return ERR_PTR(-ENOMEM);
+
+	indio_dev->name = xadc_type_names[(*ops)->type];
+	indio_dev->info = &xadc_info;
+	indio_dev->modes = INDIO_DIRECT_MODE;
+
+	return indio_dev;
+}
+
+int xadc_device_configure(struct device *dev, struct iio_dev *indio_dev, int irq,
+			  unsigned int *conf0, unsigned int *bipolar_mask)
+{
+	int ret;
+
+	ret = xadc_parse_dt(indio_dev, conf0, irq);
+	if (ret)
+		return ret;
+
+	*bipolar_mask = 0;
+	for (unsigned int i = 0; i < indio_dev->num_channels; i++) {
+		if (indio_dev->channels[i].scan_type.sign == 's')
+			*bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
+	}
+
+	return 0;
+}
+
 static void xadc_cancel_delayed_work(void *data)
 {
 	struct delayed_work *work = data;
@@ -1293,18 +1356,14 @@ static int xadc_probe(struct platform_device *pdev)
 	int irq;
 	int i;
 
-	ops = device_get_match_data(dev);
-	if (!ops)
-		return -EINVAL;
+	indio_dev = xadc_device_setup(dev, sizeof(*xadc), &ops);
+	if (IS_ERR(indio_dev))
+		return PTR_ERR(indio_dev);
 
 	irq = platform_get_irq_optional(pdev, 0);
 	if (irq < 0 && (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
 		return irq;
 
-	indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
-	if (!indio_dev)
-		return -ENOMEM;
-
 	xadc = iio_priv(indio_dev);
 	xadc->ops = ops;
 	init_completion(&xadc->completion);
@@ -1316,30 +1375,13 @@ static int xadc_probe(struct platform_device *pdev)
 	if (IS_ERR(xadc->base))
 		return PTR_ERR(xadc->base);
 
-	indio_dev->name = xadc_type_names[xadc->ops->type];
-	indio_dev->modes = INDIO_DIRECT_MODE;
-	indio_dev->info = &xadc_info;
-
-	ret = xadc_parse_dt(indio_dev, &conf0, irq);
+	ret = xadc_device_configure(dev, indio_dev, irq, &conf0, &bipolar_mask);
 	if (ret)
 		return ret;
 
-	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
-		ret = devm_iio_triggered_buffer_setup(dev, indio_dev, &iio_pollfunc_store_time,
-						      &xadc_trigger_handler, &xadc_buffer_ops);
-		if (ret)
-			return ret;
-
-		if (irq > 0) {
-			xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
-			if (IS_ERR(xadc->convst_trigger))
-				return PTR_ERR(xadc->convst_trigger);
-
-			xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev, "samplerate");
-			if (IS_ERR(xadc->samplerate_trigger))
-				return PTR_ERR(xadc->samplerate_trigger);
-		}
-	}
+	ret = xadc_setup_buffer_and_triggers(indio_dev, irq);
+	if (ret)
+		return ret;
 
 	xadc->clk = devm_clk_get_enabled(dev, NULL);
 	if (IS_ERR(xadc->clk))
-- 
2.34.1

[PATCH v3 3/6] iio: adc: xilinx-xadc: Split driver into core and platform files

[Dileep Kumar Nagavarapu]

Split the xilinx-xadc-core.c into separate core and platform specific
files to prepare for I2C interface support.

xilinx-xadc-core.c is reorganized as follows:
xilinx-xadc-core.c:
  - Platform-independent IIO/ADC operations
  - Channel definitions and management
  - Buffer and trigger management
  - Device tree parsing

xilinx-xadc-platform.c:
  - ZYNQ platform (FIFO-based) register access and interrupt handling
  - AXI platform (memory-mapped) register access and interrupt handling
  - Platform-specific setup and configuration
  - Platform device probe function

Update Kconfig to introduce XILINX_XADC_CORE as a helper module selected
by XILINX_XADC and update Makefile to build the split modules:
  - xilinx-xadc-common.o (core + events)
  - xilinx-xadc-platform.o (platform-specific)

Reorganized the code and No behavioral changes.

Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
---
 drivers/iio/adc/Kconfig                       |   8 +-
 drivers/iio/adc/Makefile                      |   5 +-
 drivers/iio/adc/xilinx-xadc-core.c            | 678 +--------------
 drivers/iio/adc/xilinx-xadc-events.c          |   1 +
 ...inx-xadc-core.c => xilinx-xadc-platform.c} | 801 +-----------------
 drivers/iio/adc/xilinx-xadc.h                 |  27 +
 6 files changed, 58 insertions(+), 1462 deletions(-)
 copy drivers/iio/adc/{xilinx-xadc-core.c => xilinx-xadc-platform.c} (45%)

diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index d1b198cb8a80..15ecf001b3ce 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -2028,11 +2028,15 @@ config VIPERBOARD_ADC
 	  To compile this driver as a module, choose M here: the module will be
 	  called viperboard_adc.
 
+config XILINX_XADC_CORE
+	tristate
+	select IIO_BUFFER
+	select IIO_TRIGGERED_BUFFER
+
 config XILINX_XADC
 	tristate "Xilinx XADC driver"
 	depends on HAS_IOMEM
-	select IIO_BUFFER
-	select IIO_TRIGGERED_BUFFER
+	select XILINX_XADC_CORE
 	help
 	  Say yes here to have support for the Xilinx 7 Series XADC or
 	  UltraScale/UltraScale+ System Management Wizard.
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 0f90b75577ff..4cb06243966c 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -175,5 +175,6 @@ obj-$(CONFIG_VERSAL_SYSMON_I2C) += versal-sysmon-i2c.o
 obj-$(CONFIG_VF610_ADC) += vf610_adc.o
 obj-$(CONFIG_VIPERBOARD_ADC) += viperboard_adc.o
 obj-$(CONFIG_XILINX_AMS) += xilinx-ams.o
-xilinx-xadc-y := xilinx-xadc-core.o xilinx-xadc-events.o
-obj-$(CONFIG_XILINX_XADC) += xilinx-xadc.o
+xilinx-xadc-common-y := xilinx-xadc-core.o xilinx-xadc-events.o
+obj-$(CONFIG_XILINX_XADC_CORE) += xilinx-xadc-common.o
+obj-$(CONFIG_XILINX_XADC) += xilinx-xadc-platform.o
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index dd1470d2bf9b..e3b1d5bebe98 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -14,558 +14,35 @@
 #include <linux/bitfield.h>
 #include <linux/bits.h>
 #include <linux/cleanup.h>
-#include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/overflow.h>
-#include <linux/platform_device.h>
 #include <linux/property.h>
 #include <linux/slab.h>
-#include <linux/sysfs.h>
 
 #include <linux/iio/buffer.h>
 #include <linux/iio/events.h>
 #include <linux/iio/iio.h>
-#include <linux/iio/sysfs.h>
 #include <linux/iio/trigger.h>
 #include <linux/iio/trigger_consumer.h>
 #include <linux/iio/triggered_buffer.h>
 
 #include "xilinx-xadc.h"
 
-static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT_MS = 500;
-
-/* ZYNQ register definitions */
-#define XADC_ZYNQ_REG_CFG	0x00
-#define XADC_ZYNQ_REG_INTSTS	0x04
-#define XADC_ZYNQ_REG_INTMSK	0x08
-#define XADC_ZYNQ_REG_STATUS	0x0c
-#define XADC_ZYNQ_REG_CFIFO	0x10
-#define XADC_ZYNQ_REG_DFIFO	0x14
-#define XADC_ZYNQ_REG_CTL		0x18
-
-#define XADC_ZYNQ_CFG_ENABLE		BIT(31)
-#define XADC_ZYNQ_CFG_CFIFOTH_MASK	GENMASK(23, 20)
-#define XADC_ZYNQ_CFG_CFIFOTH_OFFSET	20
-#define XADC_ZYNQ_CFG_DFIFOTH_MASK	GENMASK(19, 16)
-#define XADC_ZYNQ_CFG_DFIFOTH_OFFSET	16
-#define XADC_ZYNQ_CFG_WEDGE		BIT(13)
-#define XADC_ZYNQ_CFG_REDGE		BIT(12)
-#define XADC_ZYNQ_CFG_TCKRATE_MASK	GENMASK(9, 8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV2	0
-#define XADC_ZYNQ_CFG_TCKRATE_DIV4	BIT(8)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV8	BIT(9)
-#define XADC_ZYNQ_CFG_TCKRATE_DIV16	GENMASK(9, 8)
-#define XADC_ZYNQ_CFG_IGAP_MASK		GENMASK(4, 0)
-#define XADC_ZYNQ_CFG_IGAP(x)		(x)
-
-#define XADC_ZYNQ_INT_CFIFO_LTH		BIT(9)
-#define XADC_ZYNQ_INT_DFIFO_GTH		BIT(8)
-#define XADC_ZYNQ_INT_ALARM_MASK	GENMASK(7, 0)
-#define XADC_ZYNQ_INT_ALARM_OFFSET	0
-
-#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK	GENMASK(19, 16)
-#define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET	16
-#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK	GENMASK(15, 12)
-#define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET	12
-#define XADC_ZYNQ_STATUS_CFIFOF		BIT(11)
-#define XADC_ZYNQ_STATUS_CFIFOE		BIT(10)
-#define XADC_ZYNQ_STATUS_DFIFOF		BIT(9)
-#define XADC_ZYNQ_STATUS_DFIFOE		BIT(8)
-#define XADC_ZYNQ_STATUS_OT		BIT(7)
-#define XADC_ZYNQ_STATUS_ALM(x)		BIT(x)
-
-#define XADC_ZYNQ_CTL_RESET		BIT(4)
-
-#define XADC_ZYNQ_CMD_NOP		0x00
-#define XADC_ZYNQ_CMD_READ		0x01
-#define XADC_ZYNQ_CMD_WRITE		0x02
-
-#define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
-
-/* AXI register definitions */
-#define XADC_AXI_REG_RESET		0x00
-#define XADC_AXI_REG_STATUS		0x04
-#define XADC_AXI_REG_ALARM_STATUS	0x08
-#define XADC_AXI_REG_CONVST		0x0c
-#define XADC_AXI_REG_XADC_RESET		0x10
-#define XADC_AXI_REG_GIER		0x5c
-#define XADC_AXI_REG_IPISR		0x60
-#define XADC_AXI_REG_IPIER		0x68
-
-/* 7 Series */
-#define XADC_7S_AXI_ADC_REG_OFFSET	0x200
-
-/* UltraScale */
-#define XADC_US_AXI_ADC_REG_OFFSET	0x400
-
-#define XADC_AXI_RESET_MAGIC		0xa
-#define XADC_AXI_GIER_ENABLE		BIT(31)
-
-#define XADC_AXI_INT_EOS		BIT(4)
-#define XADC_AXI_INT_ALARM_MASK		(GENMASK(13, 10) | GENMASK(3, 0))
-
-#define XADC_FLAGS_BUFFERED BIT(0)
-#define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
-
-/*
- * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
- * not have a hardware FIFO. Which means an interrupt is generated for each
- * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
- * overloaded by the interrupts that it soft-lockups. For this reason the driver
- * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
- * but still responsive.
- */
-#define XADC_MAX_SAMPLERATE_SPS 150000
-
-static void xadc_write_reg(struct xadc *xadc, unsigned int reg, u32 val)
+void xadc_write_reg(struct xadc *xadc, unsigned int reg, u32 val)
 {
 	writel(val, xadc->base + reg);
 }
+EXPORT_SYMBOL_NS_GPL(xadc_write_reg, "IIO_XADC");
 
-static void xadc_read_reg(struct xadc *xadc, unsigned int reg, u32 *val)
+void xadc_read_reg(struct xadc *xadc, unsigned int reg, u32 *val)
 {
 	*val = readl(xadc->base + reg);
 }
-
-/*
- * The ZYNQ interface uses two asynchronous FIFOs for communication with the
- * XADC. Reads and writes to the XADC register are performed by submitting a
- * request to the command FIFO (CFIFO), once the request has been completed the
- * result can be read from the data FIFO (DFIFO). The method currently used in
- * this driver is to submit the request for a read/write operation, then go to
- * sleep and wait for an interrupt that signals that a response is available in
- * the data FIFO.
- */
-static void xadc_zynq_write_fifo(struct xadc *xadc, u32 *cmd, unsigned int n)
-{
-	for (unsigned int i = 0; i < n; i++)
-		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
-}
-
-static void xadc_zynq_drain_fifo(struct xadc *xadc)
-{
-	u32 status, tmp;
-
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
-
-	/*
-	 * Reading XADC_ZYNQ_REG_DFIFO pops one entry from the data FIFO.
-	 * The loop therefore removes one pending entry per iteration and
-	 * terminates once the hardware reports the FIFO empty.
-	 */
-	while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
-		xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
-		xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
-	}
-}
-
-static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask, unsigned int val)
-{
-	xadc->zynq_intmask = (xadc->zynq_intmask & ~mask) | (val & mask);
-
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask | xadc->zynq_masked_alarm);
-}
-
-static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
-{
-	u32 cmd[1];
-	u32 tmp;
-	int ret;
-
-	scoped_guard(spinlock_irq, &xadc->lock) {
-		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
-
-		reinit_completion(&xadc->completion);
-
-		cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
-		xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
-		xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
-		tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
-		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
-
-		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
-	}
-
-	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
-	if (ret == 0)
-		ret = -EIO;
-
-	if (ret < 0)
-		return ret;
-
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
-
-	return 0;
-}
-
-static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
-{
-	u32 cmd[2];
-	u32 resp, tmp;
-	int ret;
-
-	cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
-	cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
-
-	scoped_guard(spinlock_irq, &xadc->lock) {
-		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
-		xadc_zynq_drain_fifo(xadc);
-		reinit_completion(&xadc->completion);
-
-		xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
-		xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
-		tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
-		tmp |= FIELD_PREP(XADC_ZYNQ_CFG_DFIFOTH_MASK, 1);
-		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
-
-		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
-	}
-	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
-	if (ret == 0)
-		ret = -EIO;
-
-	if (ret < 0)
-		return ret;
-
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
-
-	*val = resp;
-
-	return 0;
-}
-
-static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
-{
-	/*
-	 * Reorder the Zynq PS-XADC alarm bits defined in UG585 to match the common
-	 * XADC driver alarm layout.
-	 */
-	return ((alarm & 0x80) >> 4) | ((alarm & 0x78) << 1) | (alarm & 0x07);
-}
-
-/*
- * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
- * threshold condition go way from within the interrupt handler, this means as
- * soon as a threshold condition is present we would enter the interrupt handler
- * again and again. To work around this we mask all active thresholds interrupts
- * in the interrupt handler and start a timer. In this timer we poll the
- * interrupt status and only if the interrupt is inactive we unmask it again.
- */
-static void xadc_zynq_unmask_worker(struct work_struct *work)
-{
-	struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
-	unsigned int misc_sts, unmask;
-
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
-
-	misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
-
-	scoped_guard(spinlock_irq, &xadc->lock) {
-		/* Clear those bits which are not active anymore */
-		unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
-		xadc->zynq_masked_alarm &= misc_sts;
-
-		/* Also clear those which are masked out anyway */
-		xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
-
-		/* Clear the interrupts before we unmask them */
-		xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
-
-		xadc_zynq_update_intmsk(xadc, 0, 0);
-	}
-
-	/* if still pending some alarm re-trigger the timer */
-	if (xadc->zynq_masked_alarm) {
-		schedule_delayed_work(&xadc->zynq_unmask_work,
-				      msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT_MS));
-	}
-}
-
-static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
-{
-	struct iio_dev *indio_dev = devid;
-	struct xadc *xadc = iio_priv(indio_dev);
-	u32 status;
-
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
-
-	status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
-
-	if (!status)
-		return IRQ_NONE;
-
-	guard(spinlock)(&xadc->lock);
-
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
-
-	if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
-		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
-		complete(&xadc->completion);
-	}
-
-	status &= XADC_ZYNQ_INT_ALARM_MASK;
-	if (status) {
-		xadc->zynq_masked_alarm |= status;
-		/*
-		 * mask the current event interrupt,
-		 * unmask it when the interrupt is no more active.
-		 */
-		xadc_zynq_update_intmsk(xadc, 0, 0);
-
-		xadc_handle_events(indio_dev, xadc_zynq_transform_alarm(status));
-
-		/* unmask the required interrupts in timer. */
-		schedule_delayed_work(&xadc->zynq_unmask_work,
-				      msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT_MS));
-	}
-
-	return IRQ_HANDLED;
-}
-
-#define XADC_ZYNQ_TCK_RATE_MAX_HZ 50000000
-#define XADC_ZYNQ_IGAP_DEFAULT_CYCLES 20
-#define XADC_ZYNQ_PCAP_RATE_MAX_HZ 200000000
-
-static int xadc_zynq_setup(struct platform_device *pdev, struct iio_dev *indio_dev, int irq)
-{
-	struct xadc *xadc = iio_priv(indio_dev);
-	unsigned long pcap_rate;
-	unsigned int tck_div;
-	unsigned int div;
-	unsigned int igap;
-	unsigned int tck_rate;
-	int ret;
-
-	/* TODO: Figure out how to make igap and tck_rate configurable */
-	igap = XADC_ZYNQ_IGAP_DEFAULT_CYCLES;
-	tck_rate = XADC_ZYNQ_TCK_RATE_MAX_HZ;
-
-	xadc->zynq_intmask = ~0;
-
-	pcap_rate = clk_get_rate(xadc->clk);
-	if (!pcap_rate)
-		return -EINVAL;
-
-	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX_HZ) {
-		ret = clk_set_rate(xadc->clk, (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX_HZ);
-		if (ret)
-			return ret;
-	}
-
-	if (tck_rate > pcap_rate / 2) {
-		div = 2;
-	} else {
-		div = pcap_rate / tck_rate;
-		if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX_HZ)
-			div++;
-	}
-
-	if (div <= 3)
-		tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
-	else if (div <= 7)
-		tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
-	else if (div <= 15)
-		tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
-	else
-		tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
-
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE | XADC_ZYNQ_CFG_REDGE |
-			       XADC_ZYNQ_CFG_WEDGE | tck_div | XADC_ZYNQ_CFG_IGAP(igap));
-
-	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX_HZ) {
-		ret = clk_set_rate(xadc->clk, pcap_rate);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
-{
-	unsigned int div;
-	u32 val;
-
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
-
-	switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
-	case XADC_ZYNQ_CFG_TCKRATE_DIV4:
-		div = 4;
-		break;
-	case XADC_ZYNQ_CFG_TCKRATE_DIV8:
-		div = 8;
-		break;
-	case XADC_ZYNQ_CFG_TCKRATE_DIV16:
-		div = 16;
-		break;
-	default:
-		div = 2;
-		break;
-	}
-
-	return clk_get_rate(xadc->clk) / div;
-}
-
-static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
-{
-	u32 status;
-
-	/* Move OT to bit 7 */
-	alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
-
-	guard(spinlock_irqsave)(&xadc->lock);
-
-	/* Clear previous interrupts if any. */
-	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
-	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
-
-	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK, ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
-}
-
-static const struct xadc_ops xadc_zynq_ops = {
-	.read = xadc_zynq_read_adc_reg,
-	.write = xadc_zynq_write_adc_reg,
-	.setup = xadc_zynq_setup,
-	.get_dclk_rate = xadc_zynq_get_dclk_rate,
-	.interrupt_handler = xadc_zynq_interrupt_handler,
-	.update_alarm = xadc_zynq_update_alarm,
-	.type = XADC_TYPE_S7,
-	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
-	.temp_scale = 503975,
-	.temp_offset = 273150,
-};
-
-static const unsigned int xadc_axi_reg_offsets[] = {
-	[XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
-	[XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
-};
-
-static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
-{
-	u32 val32;
-
-	xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, &val32);
-	*val = val32;
-
-	return 0;
-}
-
-static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
-{
-	xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4, val);
-
-	return 0;
-}
-
-static int xadc_axi_setup(struct platform_device *pdev, struct iio_dev *indio_dev, int irq)
-{
-	struct xadc *xadc = iio_priv(indio_dev);
-
-	xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
-	xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
-
-	return 0;
-}
-
-static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
-{
-	struct iio_dev *indio_dev = devid;
-	struct xadc *xadc = iio_priv(indio_dev);
-	u32 status, mask;
-	unsigned int events;
-
-	xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
-	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
-	status &= mask;
-
-	if (!status)
-		return IRQ_NONE;
-
-	if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
-		iio_trigger_poll(xadc->trigger);
-
-	if (status & XADC_AXI_INT_ALARM_MASK) {
-		/*
-		 * The order of the bits in the AXI-XADC status register does
-		 * not match the order of the bits in the XADC alarm enable
-		 * register. xadc_handle_events() expects the events to be in
-		 * the same order as the XADC alarm enable register.
-		 */
-		events = (status & 0x000e) >> 1;
-		events |= (status & 0x0001) << 3;
-		events |= (status & 0x3c00) >> 6;
-		xadc_handle_events(indio_dev, events);
-	}
-
-	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
-
-	return IRQ_HANDLED;
-}
-
-static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
-{
-	u32 val;
-
-	/*
-	 * The order of the bits in the AXI-XADC status register does not match
-	 * the order of the bits in the XADC alarm enable register. We get
-	 * passed the alarm mask in the same order as in the XADC alarm enable
-	 * register.
-	 */
-	alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | ((alarm & 0xf0) << 6);
-
-	guard(spinlock_irqsave)(&xadc->lock);
-	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
-	val &= ~XADC_AXI_INT_ALARM_MASK;
-	val |= alarm;
-	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
-}
-
-static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
-{
-	return clk_get_rate(xadc->clk);
-}
-
-static const struct xadc_ops xadc_7s_axi_ops = {
-	.read = xadc_axi_read_adc_reg,
-	.write = xadc_axi_write_adc_reg,
-	.setup = xadc_axi_setup,
-	.get_dclk_rate = xadc_axi_get_dclk,
-	.update_alarm = xadc_axi_update_alarm,
-	.interrupt_handler = xadc_axi_interrupt_handler,
-	.flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
-	.type = XADC_TYPE_S7,
-	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
-	.temp_scale = 503975,
-	.temp_offset = 273150,
-};
-
-static const struct xadc_ops xadc_us_axi_ops = {
-	.read = xadc_axi_read_adc_reg,
-	.write = xadc_axi_write_adc_reg,
-	.setup = xadc_axi_setup,
-	.get_dclk_rate = xadc_axi_get_dclk,
-	.update_alarm = xadc_axi_update_alarm,
-	.interrupt_handler = xadc_axi_interrupt_handler,
-	.flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
-	.type = XADC_TYPE_US,
-	/**
-	 * Values below are for UltraScale+ (SYSMONE4) using internal reference.
-	 * See https://docs.xilinx.com/v/u/en-US/ug580-ultrascale-sysmon
-	 */
-	.temp_scale = 509314,
-	.temp_offset = 280231,
-};
+EXPORT_SYMBOL_NS_GPL(xadc_read_reg, "IIO_XADC");
 
 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, u16 mask, u16 val)
 {
@@ -781,7 +258,7 @@ static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
 	return XADC_CONF1_SEQ_SIMULTANEOUS;
 }
 
-static int xadc_postdisable(struct iio_dev *indio_dev)
+int xadc_postdisable(struct iio_dev *indio_dev)
 {
 	struct xadc *xadc = iio_priv(indio_dev);
 	unsigned long scan_mask;
@@ -814,6 +291,7 @@ static int xadc_postdisable(struct iio_dev *indio_dev)
 
 	return xadc_power_adc_b(xadc, seq_mode);
 }
+EXPORT_SYMBOL_NS_GPL(xadc_postdisable, "IIO_XADC");
 
 static int xadc_preenable(struct iio_dev *indio_dev)
 {
@@ -867,7 +345,7 @@ static const struct iio_buffer_setup_ops xadc_buffer_ops = {
 	.postdisable = &xadc_postdisable,
 };
 
-static int xadc_read_samplerate(struct xadc *xadc)
+int xadc_read_samplerate(struct xadc *xadc)
 {
 	unsigned int div;
 	u16 val16;
@@ -883,6 +361,7 @@ static int xadc_read_samplerate(struct xadc *xadc)
 
 	return xadc_get_dclk_rate(xadc) / div / 26;
 }
+EXPORT_SYMBOL_NS_GPL(xadc_read_samplerate, "IIO_XADC");
 
 static int xadc_read_raw(struct iio_dev *indio_dev,
 			 struct iio_chan_spec const *chan, int *val, int *val2, long info)
@@ -977,8 +456,9 @@ int xadc_setup_buffer_and_triggers(struct iio_dev *indio_dev, int irq)
 
 	return 0;
 }
+EXPORT_SYMBOL_NS_GPL(xadc_setup_buffer_and_triggers, "IIO_XADC");
 
-static int xadc_write_samplerate(struct xadc *xadc, int val)
+int xadc_write_samplerate(struct xadc *xadc, int val)
 {
 	unsigned long clk_rate = xadc_get_dclk_rate(xadc);
 	unsigned int div;
@@ -1014,6 +494,7 @@ static int xadc_write_samplerate(struct xadc *xadc, int val)
 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
 				   div << XADC_CONF2_DIV_OFFSET);
 }
+EXPORT_SYMBOL_NS_GPL(xadc_write_samplerate, "IIO_XADC");
 
 static int xadc_write_raw(struct iio_dev *indio_dev,
 			  struct iio_chan_spec const *chan, int val, int val2, long info)
@@ -1175,21 +656,6 @@ static const struct iio_info xadc_info = {
 	.update_scan_mode = &xadc_update_scan_mode,
 };
 
-static const struct of_device_id xadc_of_match_table[] = {
-	{
-		.compatible = "xlnx,zynq-xadc-1.00.a",
-		.data = &xadc_zynq_ops
-	}, {
-		.compatible = "xlnx,axi-xadc-1.00.a",
-		.data = &xadc_7s_axi_ops
-	}, {
-		.compatible = "xlnx,system-management-wiz-1.3",
-		.data = &xadc_us_axi_ops
-	},
-	{ }
-};
-MODULE_DEVICE_TABLE(of, xadc_of_match_table);
-
 static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
 {
 	struct device *dev = indio_dev->dev.parent;
@@ -1318,6 +784,7 @@ struct iio_dev *xadc_device_setup(struct device *dev, int size, const struct xad
 
 	return indio_dev;
 }
+EXPORT_SYMBOL_NS_GPL(xadc_device_setup, "IIO_XADC");
 
 int xadc_device_configure(struct device *dev, struct iio_dev *indio_dev, int irq,
 			  unsigned int *conf0, unsigned int *bipolar_mask)
@@ -1336,125 +803,8 @@ int xadc_device_configure(struct device *dev, struct iio_dev *indio_dev, int irq
 
 	return 0;
 }
-
-static void xadc_cancel_delayed_work(void *data)
-{
-	struct delayed_work *work = data;
-
-	cancel_delayed_work_sync(work);
-}
-
-static int xadc_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	const struct xadc_ops *ops;
-	struct iio_dev *indio_dev;
-	unsigned int bipolar_mask;
-	unsigned int conf0;
-	struct xadc *xadc;
-	int ret;
-	int irq;
-	int i;
-
-	indio_dev = xadc_device_setup(dev, sizeof(*xadc), &ops);
-	if (IS_ERR(indio_dev))
-		return PTR_ERR(indio_dev);
-
-	irq = platform_get_irq_optional(pdev, 0);
-	if (irq < 0 && (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
-		return irq;
-
-	xadc = iio_priv(indio_dev);
-	xadc->ops = ops;
-	init_completion(&xadc->completion);
-	mutex_init(&xadc->mutex);
-	spin_lock_init(&xadc->lock);
-	INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
-
-	xadc->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(xadc->base))
-		return PTR_ERR(xadc->base);
-
-	ret = xadc_device_configure(dev, indio_dev, irq, &conf0, &bipolar_mask);
-	if (ret)
-		return ret;
-
-	ret = xadc_setup_buffer_and_triggers(indio_dev, irq);
-	if (ret)
-		return ret;
-
-	xadc->clk = devm_clk_get_enabled(dev, NULL);
-	if (IS_ERR(xadc->clk))
-		return PTR_ERR(xadc->clk);
-
-	/*
-	 * Make sure not to exceed the maximum samplerate since otherwise the
-	 * resulting interrupt storm will soft-lock the system.
-	 */
-	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
-		ret = xadc_read_samplerate(xadc);
-		if (ret < 0)
-			return ret;
-
-		if (ret > XADC_MAX_SAMPLERATE_SPS) {
-			ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE_SPS);
-			if (ret < 0)
-				return ret;
-		}
-	}
-
-	if (irq > 0) {
-		ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler,
-				       0, dev_name(dev), indio_dev);
-		if (ret)
-			return ret;
-
-		ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work,
-					       &xadc->zynq_unmask_work);
-		if (ret)
-			return ret;
-	}
-
-	ret = xadc->ops->setup(pdev, indio_dev, irq);
-	if (ret)
-		return ret;
-
-	for (i = 0; i < 16; i++)
-		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i), &xadc->threshold[i]);
-
-	ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
-	if (ret)
-		return ret;
-
-	bipolar_mask = 0;
-	for (i = 0; i < indio_dev->num_channels; i++) {
-		if (indio_dev->channels[i].scan_type.sign == 's')
-			bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
-	}
-
-	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
-	if (ret)
-		return ret;
-
-	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1), bipolar_mask >> 16);
-	if (ret)
-		return ret;
-
-	/* Go to non-buffered mode */
-	xadc_postdisable(indio_dev);
-
-	return devm_iio_device_register(dev, indio_dev);
-}
-
-static struct platform_driver xadc_driver = {
-	.probe = xadc_probe,
-	.driver = {
-		.name = "xadc",
-		.of_match_table = xadc_of_match_table,
-	},
-};
-module_platform_driver(xadc_driver);
+EXPORT_SYMBOL_NS_GPL(xadc_device_configure, "IIO_XADC");
 
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-MODULE_DESCRIPTION("Xilinx XADC IIO driver");
+MODULE_DESCRIPTION("Xilinx XADC IIO core driver");
diff --git a/drivers/iio/adc/xilinx-xadc-events.c b/drivers/iio/adc/xilinx-xadc-events.c
index e0e1195b7017..e66704b7d6de 100644
--- a/drivers/iio/adc/xilinx-xadc-events.c
+++ b/drivers/iio/adc/xilinx-xadc-events.c
@@ -67,6 +67,7 @@ void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events)
 	for_each_set_bit(i, &events, 8)
 		xadc_handle_event(indio_dev, i);
 }
+EXPORT_SYMBOL_NS_GPL(xadc_handle_events, "IIO_XADC");
 
 static unsigned int xadc_get_threshold_offset(const struct iio_chan_spec *chan,
 					      enum iio_event_direction dir)
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-platform.c
similarity index 45%
copy from drivers/iio/adc/xilinx-xadc-core.c
copy to drivers/iio/adc/xilinx-xadc-platform.c
index dd1470d2bf9b..38748a38da15 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-platform.c
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Xilinx XADC driver
+ * Xilinx XADC platform driver
  *
  * Copyright 2013-2014 Analog Devices Inc.
  *  Author: Lars-Peter Clausen <lars@metafoo.de>
@@ -19,21 +19,13 @@
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
 #include <linux/module.h>
-#include <linux/overflow.h>
 #include <linux/platform_device.h>
-#include <linux/property.h>
-#include <linux/slab.h>
-#include <linux/sysfs.h>
 
-#include <linux/iio/buffer.h>
 #include <linux/iio/events.h>
 #include <linux/iio/iio.h>
-#include <linux/iio/sysfs.h>
 #include <linux/iio/trigger.h>
-#include <linux/iio/trigger_consumer.h>
-#include <linux/iio/triggered_buffer.h>
 
 #include "xilinx-xadc.h"
 
@@ -94,8 +86,6 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT_MS = 500;
 #define XADC_AXI_REG_CONVST		0x0c
 #define XADC_AXI_REG_XADC_RESET		0x10
 #define XADC_AXI_REG_GIER		0x5c
-#define XADC_AXI_REG_IPISR		0x60
-#define XADC_AXI_REG_IPIER		0x68
 
 /* 7 Series */
 #define XADC_7S_AXI_ADC_REG_OFFSET	0x200
@@ -106,32 +96,8 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT_MS = 500;
 #define XADC_AXI_RESET_MAGIC		0xa
 #define XADC_AXI_GIER_ENABLE		BIT(31)
 
-#define XADC_AXI_INT_EOS		BIT(4)
 #define XADC_AXI_INT_ALARM_MASK		(GENMASK(13, 10) | GENMASK(3, 0))
 
-#define XADC_FLAGS_BUFFERED BIT(0)
-#define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
-
-/*
- * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
- * not have a hardware FIFO. Which means an interrupt is generated for each
- * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
- * overloaded by the interrupts that it soft-lockups. For this reason the driver
- * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
- * but still responsive.
- */
-#define XADC_MAX_SAMPLERATE_SPS 150000
-
-static void xadc_write_reg(struct xadc *xadc, unsigned int reg, u32 val)
-{
-	writel(val, xadc->base + reg);
-}
-
-static void xadc_read_reg(struct xadc *xadc, unsigned int reg, u32 *val)
-{
-	*val = readl(xadc->base + reg);
-}
-
 /*
  * The ZYNQ interface uses two asynchronous FIFOs for communication with the
  * XADC. Reads and writes to the XADC register are performed by submitting a
@@ -567,614 +533,6 @@ static const struct xadc_ops xadc_us_axi_ops = {
 	.temp_offset = 280231,
 };
 
-static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, u16 mask, u16 val)
-{
-	u16 tmp;
-	int ret;
-
-	ret = _xadc_read_adc_reg(xadc, reg, &tmp);
-	if (ret)
-		return ret;
-
-	return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
-}
-
-static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, u16 mask, u16 val)
-{
-	int ret;
-
-	mutex_lock(&xadc->mutex);
-	ret = _xadc_update_adc_reg(xadc, reg, mask, val);
-	mutex_unlock(&xadc->mutex);
-
-	return ret;
-}
-
-static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
-{
-	return xadc->ops->get_dclk_rate(xadc);
-}
-
-static int xadc_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *mask)
-{
-	struct xadc *xadc = iio_priv(indio_dev);
-	void *data;
-	size_t n;
-
-	n = bitmap_weight(mask, iio_get_masklength(indio_dev));
-
-	data = devm_krealloc_array(indio_dev->dev.parent, xadc->data, n,
-				   sizeof(*xadc->data), GFP_KERNEL);
-	if (!data)
-		return -ENOMEM;
-
-	memset(data, 0, n * sizeof(*xadc->data));
-	xadc->data = data;
-
-	return 0;
-}
-
-static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
-{
-	switch (scan_index) {
-	case 5:
-		return XADC_REG_VCCPINT;
-	case 6:
-		return XADC_REG_VCCPAUX;
-	case 7:
-		return XADC_REG_VCCO_DDR;
-	case 8:
-		return XADC_REG_TEMP;
-	case 9:
-		return XADC_REG_VCCINT;
-	case 10:
-		return XADC_REG_VCCAUX;
-	case 11:
-		return XADC_REG_VPVN;
-	case 12:
-		return XADC_REG_VREFP;
-	case 13:
-		return XADC_REG_VREFN;
-	case 14:
-		return XADC_REG_VCCBRAM;
-	default:
-		return XADC_REG_VAUX(scan_index - 16);
-	}
-}
-
-static irqreturn_t xadc_trigger_handler(int irq, void *p)
-{
-	struct iio_poll_func *pf = p;
-	struct iio_dev *indio_dev = pf->indio_dev;
-	struct xadc *xadc = iio_priv(indio_dev);
-	unsigned int chan;
-	int i, j;
-
-	if (!xadc->data)
-		goto out;
-
-	j = 0;
-	iio_for_each_active_channel(indio_dev, i) {
-		chan = xadc_scan_index_to_channel(i);
-		xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
-		j++;
-	}
-
-	iio_push_to_buffers(indio_dev, xadc->data);
-
-out:
-	iio_trigger_notify_done(indio_dev->trig);
-
-	return IRQ_HANDLED;
-}
-
-static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
-{
-	struct xadc *xadc = iio_trigger_get_drvdata(trigger);
-	unsigned int convst;
-	unsigned int val;
-	int ret = 0;
-
-	mutex_lock(&xadc->mutex);
-
-	if (state) {
-		/* Only one of the two triggers can be active at a time. */
-		if (xadc->trigger) {
-			ret = -EBUSY;
-			goto err_out;
-		} else {
-			xadc->trigger = trigger;
-			if (trigger == xadc->convst_trigger)
-				convst = XADC_CONF0_EC;
-			else
-				convst = 0;
-		}
-		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC, convst);
-		if (ret)
-			goto err_out;
-	} else {
-		xadc->trigger = NULL;
-	}
-
-	scoped_guard(spinlock_irqsave, &xadc->lock) {
-		xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
-		xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
-		if (state)
-			val |= XADC_AXI_INT_EOS;
-		else
-			val &= ~XADC_AXI_INT_EOS;
-		xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
-	}
-
-err_out:
-	mutex_unlock(&xadc->mutex);
-
-	return ret;
-}
-
-static const struct iio_trigger_ops xadc_trigger_ops = {
-	.set_trigger_state = &xadc_trigger_set_state,
-};
-
-static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev, const char *name)
-{
-	struct device *dev = indio_dev->dev.parent;
-	struct iio_trigger *trig;
-	int ret;
-
-	trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
-				      iio_device_id(indio_dev), name);
-	if (!trig)
-		return ERR_PTR(-ENOMEM);
-
-	trig->ops = &xadc_trigger_ops;
-	iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
-
-	ret = devm_iio_trigger_register(dev, trig);
-	if (ret)
-		return ERR_PTR(ret);
-
-	return trig;
-}
-
-static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
-{
-	u16 val;
-
-	/*
-	 * As per datasheet the power-down bits are don't care in the
-	 * UltraScale, but as per reality setting the power-down bit for the
-	 * non-existing ADC-B powers down the main ADC, so just return and don't
-	 * do anything.
-	 */
-	if (xadc->ops->type == XADC_TYPE_US)
-		return 0;
-
-	/* Powerdown the ADC-B when it is not needed. */
-	switch (seq_mode) {
-	case XADC_CONF1_SEQ_SIMULTANEOUS:
-	case XADC_CONF1_SEQ_INDEPENDENT:
-		val = 0;
-		break;
-	default:
-		val = XADC_CONF2_PD_ADC_B;
-		break;
-	}
-
-	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK, val);
-}
-
-static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
-{
-	unsigned int aux_scan_mode = scan_mode >> 16;
-
-	/* UltraScale has only one ADC and supports only continuous mode */
-	if (xadc->ops->type == XADC_TYPE_US)
-		return XADC_CONF1_SEQ_CONTINUOUS;
-
-	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
-		return XADC_CONF1_SEQ_SIMULTANEOUS;
-
-	if (!(aux_scan_mode & 0xff00) || !(aux_scan_mode & 0x00ff))
-		return XADC_CONF1_SEQ_CONTINUOUS;
-
-	return XADC_CONF1_SEQ_SIMULTANEOUS;
-}
-
-static int xadc_postdisable(struct iio_dev *indio_dev)
-{
-	struct xadc *xadc = iio_priv(indio_dev);
-	unsigned long scan_mask;
-	int seq_mode;
-	int ret;
-	int i;
-
-	scan_mask = 1; /* Run calibration as part of the sequence */
-	for (i = 0; i < indio_dev->num_channels; i++)
-		scan_mask |= BIT(indio_dev->channels[i].scan_index);
-
-	/*
-	 * Use the correct sequencer mode for the idle state: simultaneous
-	 * mode for dual external mux configurations, continuous otherwise.
-	 */
-	seq_mode = xadc_get_seq_mode(xadc, scan_mask);
-
-	/* Enable all channels and calibration */
-	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
-	if (ret)
-		return ret;
-
-	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
-	if (ret)
-		return ret;
-
-	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, seq_mode);
-	if (ret)
-		return ret;
-
-	return xadc_power_adc_b(xadc, seq_mode);
-}
-
-static int xadc_preenable(struct iio_dev *indio_dev)
-{
-	struct xadc *xadc = iio_priv(indio_dev);
-	unsigned long scan_mask;
-	int seq_mode;
-	int ret;
-
-	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
-				  XADC_CONF1_SEQ_DEFAULT);
-	if (ret)
-		goto err;
-
-	scan_mask = *indio_dev->active_scan_mask;
-	seq_mode = xadc_get_seq_mode(xadc, scan_mask);
-
-	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
-	if (ret)
-		goto err;
-
-	/*
-	 * In simultaneous mode the upper and lower aux channels are samples at
-	 * the same time. In this mode the upper 8 bits in the sequencer
-	 * register are don't care and the lower 8 bits control two channels
-	 * each. As such we must set the bit if either the channel in the lower
-	 * group or the upper group is enabled.
-	 */
-	if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
-		scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
-
-	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
-	if (ret)
-		goto err;
-
-	ret = xadc_power_adc_b(xadc, seq_mode);
-	if (ret)
-		goto err;
-
-	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, seq_mode);
-	if (ret)
-		goto err;
-
-	return 0;
-err:
-	xadc_postdisable(indio_dev);
-	return ret;
-}
-
-static const struct iio_buffer_setup_ops xadc_buffer_ops = {
-	.preenable = &xadc_preenable,
-	.postdisable = &xadc_postdisable,
-};
-
-static int xadc_read_samplerate(struct xadc *xadc)
-{
-	unsigned int div;
-	u16 val16;
-	int ret;
-
-	ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
-	if (ret)
-		return ret;
-
-	div = FIELD_GET(XADC_CONF2_DIV_MASK, val16);
-	if (div < 2)
-		div = 2;
-
-	return xadc_get_dclk_rate(xadc) / div / 26;
-}
-
-static int xadc_read_raw(struct iio_dev *indio_dev,
-			 struct iio_chan_spec const *chan, int *val, int *val2, long info)
-{
-	struct xadc *xadc = iio_priv(indio_dev);
-	unsigned int bits = chan->scan_type.realbits;
-	u16 val16;
-	int ret;
-
-	switch (info) {
-	case IIO_CHAN_INFO_RAW:
-		if (iio_buffer_enabled(indio_dev))
-			return -EBUSY;
-		ret = xadc_read_adc_reg(xadc, chan->address, &val16);
-		if (ret < 0)
-			return ret;
-
-		val16 >>= chan->scan_type.shift;
-		if (chan->scan_type.sign == 'u')
-			*val = val16;
-		else
-			*val = sign_extend32(val16, bits - 1);
-
-		return IIO_VAL_INT;
-	case IIO_CHAN_INFO_SCALE:
-		switch (chan->type) {
-		case IIO_VOLTAGE:
-			/* V = (val * 3.0) / 2**bits */
-			switch (chan->address) {
-			case XADC_REG_VCCINT:
-			case XADC_REG_VCCAUX:
-			case XADC_REG_VREFP:
-			case XADC_REG_VREFN:
-			case XADC_REG_VCCBRAM:
-			case XADC_REG_VCCPINT:
-			case XADC_REG_VCCPAUX:
-			case XADC_REG_VCCO_DDR:
-				*val = 3000;
-				break;
-			default:
-				*val = 1000;
-				break;
-			}
-			*val2 = bits;
-			return IIO_VAL_FRACTIONAL_LOG2;
-		case IIO_TEMP:
-			*val = xadc->ops->temp_scale;
-			*val2 = bits;
-			return IIO_VAL_FRACTIONAL_LOG2;
-		default:
-			return -EINVAL;
-		}
-	case IIO_CHAN_INFO_OFFSET:
-		/* Only the temperature channel has an offset */
-		*val = -((xadc->ops->temp_offset << bits) / xadc->ops->temp_scale);
-		return IIO_VAL_INT;
-	case IIO_CHAN_INFO_SAMP_FREQ:
-		ret = xadc_read_samplerate(xadc);
-		if (ret < 0)
-			return ret;
-
-		*val = ret;
-		return IIO_VAL_INT;
-	default:
-		return -EINVAL;
-	}
-}
-
-int xadc_setup_buffer_and_triggers(struct iio_dev *indio_dev, int irq)
-{
-	struct xadc *xadc = iio_priv(indio_dev);
-	struct device *dev = indio_dev->dev.parent;
-	int ret;
-
-	if (!(xadc->ops->flags & XADC_FLAGS_BUFFERED))
-		return 0;
-
-	ret = devm_iio_triggered_buffer_setup(dev, indio_dev, &iio_pollfunc_store_time,
-					      &xadc_trigger_handler, &xadc_buffer_ops);
-	if (ret)
-		return ret;
-
-	if (irq > 0) {
-		xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
-		if (IS_ERR(xadc->convst_trigger))
-			return PTR_ERR(xadc->convst_trigger);
-
-		xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev, "samplerate");
-		if (IS_ERR(xadc->samplerate_trigger))
-			return PTR_ERR(xadc->samplerate_trigger);
-	}
-
-	return 0;
-}
-
-static int xadc_write_samplerate(struct xadc *xadc, int val)
-{
-	unsigned long clk_rate = xadc_get_dclk_rate(xadc);
-	unsigned int div;
-
-	if (!clk_rate)
-		return -EINVAL;
-
-	if (val <= 0)
-		return -EINVAL;
-
-	/* Max. 150 kSPS */
-	if (val > XADC_MAX_SAMPLERATE_SPS)
-		val = XADC_MAX_SAMPLERATE_SPS;
-
-	val *= 26;
-
-	/* Min 1MHz */
-	if (val < 1000000)
-		val = 1000000;
-
-	/*
-	 * We want to round down, but only if we do not exceed the 150 kSPS
-	 * limit.
-	 */
-	div = clk_rate / val;
-	if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE_SPS)
-		div++;
-	if (div < 2)
-		div = 2;
-	else if (div > 0xff)
-		div = 0xff;
-
-	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
-				   div << XADC_CONF2_DIV_OFFSET);
-}
-
-static int xadc_write_raw(struct iio_dev *indio_dev,
-			  struct iio_chan_spec const *chan, int val, int val2, long info)
-{
-	struct xadc *xadc = iio_priv(indio_dev);
-
-	if (info != IIO_CHAN_INFO_SAMP_FREQ)
-		return -EINVAL;
-
-	return xadc_write_samplerate(xadc, val);
-}
-
-static const struct iio_event_spec xadc_temp_events[] = {
-	{
-		.type = IIO_EV_TYPE_THRESH,
-		.dir = IIO_EV_DIR_RISING,
-		.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
-				 BIT(IIO_EV_INFO_VALUE) |
-				 BIT(IIO_EV_INFO_HYSTERESIS),
-	},
-};
-
-/* Separate values for upper and lower thresholds, but only a shared enabled */
-static const struct iio_event_spec xadc_voltage_events[] = {
-	{
-		.type = IIO_EV_TYPE_THRESH,
-		.dir = IIO_EV_DIR_RISING,
-		.mask_separate = BIT(IIO_EV_INFO_VALUE),
-	}, {
-		.type = IIO_EV_TYPE_THRESH,
-		.dir = IIO_EV_DIR_FALLING,
-		.mask_separate = BIT(IIO_EV_INFO_VALUE),
-	}, {
-		.type = IIO_EV_TYPE_THRESH,
-		.dir = IIO_EV_DIR_EITHER,
-		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
-	},
-};
-
-#define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
-	.type = IIO_TEMP, \
-	.indexed = 1, \
-	.channel = (_chan), \
-	.address = (_addr), \
-	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
-		BIT(IIO_CHAN_INFO_SCALE) | \
-		BIT(IIO_CHAN_INFO_OFFSET), \
-	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
-	.event_spec = xadc_temp_events, \
-	.num_event_specs = ARRAY_SIZE(xadc_temp_events), \
-	.scan_index = (_scan_index), \
-	.scan_type = { \
-		.sign = 'u', \
-		.realbits = (_bits), \
-		.storagebits = 16, \
-		.shift = 16 - (_bits), \
-		.endianness = IIO_CPU, \
-	}, \
-}
-
-#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
-	.type = IIO_VOLTAGE, \
-	.indexed = 1, \
-	.channel = (_chan), \
-	.address = (_addr), \
-	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
-		BIT(IIO_CHAN_INFO_SCALE), \
-	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
-	.event_spec = (_alarm) ? xadc_voltage_events : NULL, \
-	.num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
-	.scan_index = (_scan_index), \
-	.scan_type = { \
-		.sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
-		.realbits = (_bits), \
-		.storagebits = 16, \
-		.shift = 16 - (_bits), \
-		.endianness = IIO_CPU, \
-	}, \
-	.extend_name = _ext, \
-}
-
-/* 7 Series */
-#define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
-	XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
-#define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
-	XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
-
-static const struct iio_chan_spec xadc_7s_channels[] = {
-	XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
-	XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
-	XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
-	XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
-	XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
-	XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
-	XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
-	XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
-	XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
-	XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
-	XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
-	XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
-};
-
-/* UltraScale */
-#define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
-	XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
-#define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
-	XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
-
-static const struct iio_chan_spec xadc_us_channels[] = {
-	XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
-	XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
-	XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
-	XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
-	XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
-	XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
-	XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
-	XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
-	XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
-	XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
-	XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
-	XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
-	XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
-	XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
-	XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
-	XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
-	XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
-	XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
-	XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
-	XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
-	XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
-	XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
-	XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
-	XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
-	XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
-	XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
-};
-
-static const struct iio_info xadc_info = {
-	.read_raw = &xadc_read_raw,
-	.write_raw = &xadc_write_raw,
-	.read_event_config = &xadc_read_event_config,
-	.write_event_config = &xadc_write_event_config,
-	.read_event_value = &xadc_read_event_value,
-	.write_event_value = &xadc_write_event_value,
-	.update_scan_mode = &xadc_update_scan_mode,
-};
-
 static const struct of_device_id xadc_of_match_table[] = {
 	{
 		.compatible = "xlnx,zynq-xadc-1.00.a",
@@ -1190,153 +548,6 @@ static const struct of_device_id xadc_of_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, xadc_of_match_table);
 
-static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
-{
-	struct device *dev = indio_dev->dev.parent;
-	struct xadc *xadc = iio_priv(indio_dev);
-	const struct iio_chan_spec *channel_templates;
-	struct iio_chan_spec *channels, *chan;
-	struct fwnode_handle *chan_node, *child;
-	unsigned int max_channels;
-	unsigned int num_channels;
-	const char *external_mux;
-	u32 ext_mux_chan;
-	u32 reg;
-	int ret;
-	int i;
-
-	*conf = 0;
-
-	ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux);
-	if (ret < 0 || strcasecmp(external_mux, "none") == 0)
-		xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
-	else if (strcasecmp(external_mux, "single") == 0)
-		xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
-	else if (strcasecmp(external_mux, "dual") == 0)
-		xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
-	else
-		return -EINVAL;
-
-	if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
-		ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan);
-		if (ret < 0)
-			return ret;
-
-		if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
-			if (ext_mux_chan == 0)
-				ext_mux_chan = XADC_REG_VPVN;
-			else if (ext_mux_chan <= 16)
-				ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
-			else
-				return -EINVAL;
-		} else {
-			if (ext_mux_chan > 0 && ext_mux_chan <= 8)
-				ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
-			else
-				return -EINVAL;
-		}
-
-		*conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
-	}
-	if (xadc->ops->type == XADC_TYPE_S7) {
-		channel_templates = xadc_7s_channels;
-		max_channels = ARRAY_SIZE(xadc_7s_channels);
-	} else {
-		channel_templates = xadc_us_channels;
-		max_channels = ARRAY_SIZE(xadc_us_channels);
-	}
-	channels = devm_kmemdup_array(dev, channel_templates, max_channels,
-				      sizeof(*channel_templates), GFP_KERNEL);
-	if (!channels)
-		return -ENOMEM;
-
-	num_channels = 9;
-	chan = &channels[9];
-
-	chan_node = device_get_named_child_node(dev, "xlnx,channels");
-	fwnode_for_each_child_node(chan_node, child) {
-		if (num_channels >= max_channels) {
-			fwnode_handle_put(child);
-			break;
-		}
-
-		ret = fwnode_property_read_u32(child, "reg", &reg);
-		if (ret || reg > 16)
-			continue;
-
-		if (fwnode_property_read_bool(child, "xlnx,bipolar"))
-			chan->scan_type.sign = 's';
-
-		if (reg == 0) {
-			chan->scan_index = 11;
-			chan->address = XADC_REG_VPVN;
-		} else {
-			chan->scan_index = 15 + reg;
-			chan->address = XADC_REG_VAUX(reg - 1);
-		}
-		num_channels++;
-		chan++;
-	}
-	fwnode_handle_put(chan_node);
-
-	/* No IRQ => no events */
-	if (irq <= 0) {
-		for (i = 0; i < num_channels; i++) {
-			channels[i].event_spec = NULL;
-			channels[i].num_event_specs = 0;
-		}
-	}
-
-	indio_dev->num_channels = num_channels;
-	indio_dev->channels = devm_krealloc_array(dev, channels, num_channels,
-						  sizeof(*channels), GFP_KERNEL);
-	/* If we can't resize the channels array, just use the original */
-	if (!indio_dev->channels)
-		indio_dev->channels = channels;
-
-	return 0;
-}
-
-static const char *const xadc_type_names[] = {
-	[XADC_TYPE_S7] = "xadc",
-	[XADC_TYPE_US] = "xilinx-system-monitor",
-};
-
-struct iio_dev *xadc_device_setup(struct device *dev, int size, const struct xadc_ops **ops)
-{
-	struct iio_dev *indio_dev;
-
-	*ops = device_get_match_data(dev);
-
-	indio_dev = devm_iio_device_alloc(dev, size);
-	if (!indio_dev)
-		return ERR_PTR(-ENOMEM);
-
-	indio_dev->name = xadc_type_names[(*ops)->type];
-	indio_dev->info = &xadc_info;
-	indio_dev->modes = INDIO_DIRECT_MODE;
-
-	return indio_dev;
-}
-
-int xadc_device_configure(struct device *dev, struct iio_dev *indio_dev, int irq,
-			  unsigned int *conf0, unsigned int *bipolar_mask)
-{
-	int ret;
-
-	ret = xadc_parse_dt(indio_dev, conf0, irq);
-	if (ret)
-		return ret;
-
-	*bipolar_mask = 0;
-	for (unsigned int i = 0; i < indio_dev->num_channels; i++) {
-		if (indio_dev->channels[i].scan_type.sign == 's')
-			*bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
-	}
-
-	return 0;
-}
-
 static void xadc_cancel_delayed_work(void *data)
 {
 	struct delayed_work *work = data;
@@ -1455,6 +666,8 @@ static struct platform_driver xadc_driver = {
 };
 module_platform_driver(xadc_driver);
 
-MODULE_LICENSE("GPL v2");
+MODULE_IMPORT_NS("IIO_XADC");
+
+MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-MODULE_DESCRIPTION("Xilinx XADC IIO driver");
+MODULE_DESCRIPTION("Xilinx XADC platform driver");
diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h
index 7830135a499f..3a9cc87c43b5 100644
--- a/drivers/iio/adc/xilinx-xadc.h
+++ b/drivers/iio/adc/xilinx-xadc.h
@@ -203,4 +203,31 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 va
 #define XADC_THRESHOLD_VCCPAUX_MIN	0xe
 #define XADC_THRESHOLD_VCCODDR_MIN	0xf
 
+/*
+ * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
+ * not have a hardware FIFO. Which means an interrupt is generated for each
+ * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
+ * overloaded by the interrupts that it soft-lockups. For this reason the driver
+ * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
+ * but still responsive.
+ */
+#define XADC_MAX_SAMPLERATE_SPS 150000
+
+#define XADC_FLAGS_BUFFERED BIT(0)
+#define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
+
+#define XADC_AXI_REG_IPISR		0x60
+#define XADC_AXI_REG_IPIER		0x68
+#define XADC_AXI_INT_EOS		BIT(4)
+
+void xadc_write_reg(struct xadc *xadc, unsigned int reg, uint32_t val);
+void xadc_read_reg(struct xadc *xadc, unsigned int reg, uint32_t *val);
+struct iio_dev *xadc_device_setup(struct device *dev, int size, const struct xadc_ops **ops);
+int xadc_device_configure(struct device *dev, struct iio_dev *indio_dev,
+			  int irq, unsigned int *conf0, unsigned int *bipolar_mask);
+int xadc_read_samplerate(struct xadc *xadc);
+int xadc_write_samplerate(struct xadc *xadc, int val);
+int xadc_setup_buffer_and_triggers(struct iio_dev *indio_dev, int irq);
+int xadc_postdisable(struct iio_dev *indio_dev);
+
 #endif
-- 
2.34.1

Re: [PATCH v3 3/6] iio: adc: xilinx-xadc: Split driver into core and platform files

[Uwe Kleine-König]

[-- Attachment #1: Type: text/plain, Size: 670 bytes --]

Hello,

On Wed, Jul 29, 2026 at 06:24:52PM +0530, Dileep Kumar Nagavarapu wrote:
> @@ -19,21 +19,13 @@
>  #include <linux/err.h>
>  #include <linux/interrupt.h>
>  #include <linux/io.h>
> -#include <linux/kernel.h>
> +#include <linux/mod_devicetable.h>

I wonder why so many people recently add <linux/mod_devicetable.h> in
their patches. Is there some tool that suggests that?

Anyhow: Please don't. <linux/platform_device.h> is already enough to get
of_device_id (which is the only *_device_id this driver is using unless
I missed something).

linux/mod_devicetable.h will hopefully go away soon, so each patch
adding an #include for it is annoying.

Best regards
Uwe

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[PATCH v3 4/6] iio: adc: xilinx-xadc: Add .setup_channels() to struct xadc_ops

[Dileep Kumar Nagavarapu]

Add .setup_channels() function pointer to struct xadc_ops to enable
different interfaces to have custom channel setup logic.

Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
---
 drivers/iio/adc/xilinx-xadc-core.c     | 6 ++++--
 drivers/iio/adc/xilinx-xadc-platform.c | 3 +++
 drivers/iio/adc/xilinx-xadc.h          | 2 ++
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index e3b1d5bebe98..d39ff54439ba 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -656,7 +656,7 @@ static const struct iio_info xadc_info = {
 	.update_scan_mode = &xadc_update_scan_mode,
 };
 
-static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
+int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
 {
 	struct device *dev = indio_dev->dev.parent;
 	struct xadc *xadc = iio_priv(indio_dev);
@@ -762,6 +762,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
 
 	return 0;
 }
+EXPORT_SYMBOL_NS_GPL(xadc_parse_dt, "IIO_XADC");
 
 static const char *const xadc_type_names[] = {
 	[XADC_TYPE_S7] = "xadc",
@@ -789,9 +790,10 @@ EXPORT_SYMBOL_NS_GPL(xadc_device_setup, "IIO_XADC");
 int xadc_device_configure(struct device *dev, struct iio_dev *indio_dev, int irq,
 			  unsigned int *conf0, unsigned int *bipolar_mask)
 {
+	struct xadc *xadc = iio_priv(indio_dev);
 	int ret;
 
-	ret = xadc_parse_dt(indio_dev, conf0, irq);
+	ret = xadc->ops->setup_channels(indio_dev, conf0, irq);
 	if (ret)
 		return ret;
 
diff --git a/drivers/iio/adc/xilinx-xadc-platform.c b/drivers/iio/adc/xilinx-xadc-platform.c
index 38748a38da15..bd033315c72f 100644
--- a/drivers/iio/adc/xilinx-xadc-platform.c
+++ b/drivers/iio/adc/xilinx-xadc-platform.c
@@ -405,6 +405,7 @@ static const struct xadc_ops xadc_zynq_ops = {
 	.get_dclk_rate = xadc_zynq_get_dclk_rate,
 	.interrupt_handler = xadc_zynq_interrupt_handler,
 	.update_alarm = xadc_zynq_update_alarm,
+	.setup_channels = xadc_parse_dt,
 	.type = XADC_TYPE_S7,
 	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
 	.temp_scale = 503975,
@@ -509,6 +510,7 @@ static const struct xadc_ops xadc_7s_axi_ops = {
 	.get_dclk_rate = xadc_axi_get_dclk,
 	.update_alarm = xadc_axi_update_alarm,
 	.interrupt_handler = xadc_axi_interrupt_handler,
+	.setup_channels = xadc_parse_dt,
 	.flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
 	.type = XADC_TYPE_S7,
 	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
@@ -523,6 +525,7 @@ static const struct xadc_ops xadc_us_axi_ops = {
 	.get_dclk_rate = xadc_axi_get_dclk,
 	.update_alarm = xadc_axi_update_alarm,
 	.interrupt_handler = xadc_axi_interrupt_handler,
+	.setup_channels = xadc_parse_dt,
 	.flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
 	.type = XADC_TYPE_US,
 	/**
diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h
index 3a9cc87c43b5..67efa093157e 100644
--- a/drivers/iio/adc/xilinx-xadc.h
+++ b/drivers/iio/adc/xilinx-xadc.h
@@ -78,6 +78,7 @@ struct xadc_ops {
 	void (*update_alarm)(struct xadc *xadc, unsigned int alarm);
 	unsigned long (*get_dclk_rate)(struct xadc *xadc);
 	irqreturn_t (*interrupt_handler)(int irq, void *devid);
+	int (*setup_channels)(struct iio_dev *indio_dev, unsigned int *conf, int irq);
 
 	unsigned int flags;
 	enum xadc_type type;
@@ -223,6 +224,7 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 va
 void xadc_write_reg(struct xadc *xadc, unsigned int reg, uint32_t val);
 void xadc_read_reg(struct xadc *xadc, unsigned int reg, uint32_t *val);
 struct iio_dev *xadc_device_setup(struct device *dev, int size, const struct xadc_ops **ops);
+int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq);
 int xadc_device_configure(struct device *dev, struct iio_dev *indio_dev,
 			  int irq, unsigned int *conf0, unsigned int *bipolar_mask);
 int xadc_read_samplerate(struct xadc *xadc);
-- 
2.34.1

Re: [PATCH v3 4/6] iio: adc: xilinx-xadc: Add .setup_channels() to struct xadc_ops

[David Lechner]

On 7/29/26 7:54 AM, Dileep Kumar Nagavarapu wrote:
> Add .setup_channels() function pointer to struct xadc_ops to enable
> different interfaces to have custom channel setup logic.
> 
> Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
> ---
>  drivers/iio/adc/xilinx-xadc-core.c     | 6 ++++--
>  drivers/iio/adc/xilinx-xadc-platform.c | 3 +++
>  drivers/iio/adc/xilinx-xadc.h          | 2 ++
>  3 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
> index e3b1d5bebe98..d39ff54439ba 100644
> --- a/drivers/iio/adc/xilinx-xadc-core.c
> +++ b/drivers/iio/adc/xilinx-xadc-core.c
> @@ -656,7 +656,7 @@ static const struct iio_info xadc_info = {
>  	.update_scan_mode = &xadc_update_scan_mode,
>  };
>  
> -static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
> +int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
>  {
>  	struct device *dev = indio_dev->dev.parent;
>  	struct xadc *xadc = iio_priv(indio_dev);
> @@ -762,6 +762,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
>  
>  	return 0;
>  }
> +EXPORT_SYMBOL_NS_GPL(xadc_parse_dt, "IIO_XADC");

This function is only used once. Would be better to just move
it to the file that uses it instead of making a public function.

>  
>  static const char *const xadc_type_names[] = {
>  	[XADC_TYPE_S7] = "xadc",
> @@ -789,9 +790,10 @@ EXPORT_SYMBOL_NS_GPL(xadc_device_setup, "IIO_XADC");
>  int xadc_device_configure(struct device *dev, struct iio_dev *indio_dev, int irq,
>  			  unsigned int *conf0, unsigned int *bipolar_mask)
>  {
> +	struct xadc *xadc = iio_priv(indio_dev);
>  	int ret;
>  
> -	ret = xadc_parse_dt(indio_dev, conf0, irq);
> +	ret = xadc->ops->setup_channels(indio_dev, conf0, irq);
>  	if (ret)
>  		return ret;
>  
> diff --git a/drivers/iio/adc/xilinx-xadc-platform.c b/drivers/iio/adc/xilinx-xadc-platform.c
> index 38748a38da15..bd033315c72f 100644
> --- a/drivers/iio/adc/xilinx-xadc-platform.c
> +++ b/drivers/iio/adc/xilinx-xadc-platform.c
> @@ -405,6 +405,7 @@ static const struct xadc_ops xadc_zynq_ops = {
>  	.get_dclk_rate = xadc_zynq_get_dclk_rate,
>  	.interrupt_handler = xadc_zynq_interrupt_handler,
>  	.update_alarm = xadc_zynq_update_alarm,
> +	.setup_channels = xadc_parse_dt,
>  	.type = XADC_TYPE_S7,
>  	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
>  	.temp_scale = 503975,
> @@ -509,6 +510,7 @@ static const struct xadc_ops xadc_7s_axi_ops = {
>  	.get_dclk_rate = xadc_axi_get_dclk,
>  	.update_alarm = xadc_axi_update_alarm,
>  	.interrupt_handler = xadc_axi_interrupt_handler,
> +	.setup_channels = xadc_parse_dt,
>  	.flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
>  	.type = XADC_TYPE_S7,
>  	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
> @@ -523,6 +525,7 @@ static const struct xadc_ops xadc_us_axi_ops = {
>  	.get_dclk_rate = xadc_axi_get_dclk,
>  	.update_alarm = xadc_axi_update_alarm,
>  	.interrupt_handler = xadc_axi_interrupt_handler,
> +	.setup_channels = xadc_parse_dt,
>  	.flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
>  	.type = XADC_TYPE_US,
>  	/**
> diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h
> index 3a9cc87c43b5..67efa093157e 100644
> --- a/drivers/iio/adc/xilinx-xadc.h
> +++ b/drivers/iio/adc/xilinx-xadc.h
> @@ -78,6 +78,7 @@ struct xadc_ops {
>  	void (*update_alarm)(struct xadc *xadc, unsigned int alarm);
>  	unsigned long (*get_dclk_rate)(struct xadc *xadc);
>  	irqreturn_t (*interrupt_handler)(int irq, void *devid);
> +	int (*setup_channels)(struct iio_dev *indio_dev, unsigned int *conf, int irq);
>  
>  	unsigned int flags;
>  	enum xadc_type type;
> @@ -223,6 +224,7 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 va
>  void xadc_write_reg(struct xadc *xadc, unsigned int reg, uint32_t val);
>  void xadc_read_reg(struct xadc *xadc, unsigned int reg, uint32_t *val);
>  struct iio_dev *xadc_device_setup(struct device *dev, int size, const struct xadc_ops **ops);
> +int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq);
>  int xadc_device_configure(struct device *dev, struct iio_dev *indio_dev,
>  			  int irq, unsigned int *conf0, unsigned int *bipolar_mask);
>  int xadc_read_samplerate(struct xadc *xadc);

Re: [PATCH v3 4/6] iio: adc: xilinx-xadc: Add .setup_channels() to struct xadc_ops

[David Lechner]

On 8/1/26 11:47 AM, David Lechner wrote:
> On 7/29/26 7:54 AM, Dileep Kumar Nagavarapu wrote:
>> Add .setup_channels() function pointer to struct xadc_ops to enable
>> different interfaces to have custom channel setup logic.
>>
>> Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
>> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
>> Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
>> ---
>>  drivers/iio/adc/xilinx-xadc-core.c     | 6 ++++--
>>  drivers/iio/adc/xilinx-xadc-platform.c | 3 +++
>>  drivers/iio/adc/xilinx-xadc.h          | 2 ++
>>  3 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
>> index e3b1d5bebe98..d39ff54439ba 100644
>> --- a/drivers/iio/adc/xilinx-xadc-core.c
>> +++ b/drivers/iio/adc/xilinx-xadc-core.c
>> @@ -656,7 +656,7 @@ static const struct iio_info xadc_info = {
>>  	.update_scan_mode = &xadc_update_scan_mode,
>>  };
>>  
>> -static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
>> +int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
>>  {
>>  	struct device *dev = indio_dev->dev.parent;
>>  	struct xadc *xadc = iio_priv(indio_dev);
>> @@ -762,6 +762,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
>>  
>>  	return 0;
>>  }
>> +EXPORT_SYMBOL_NS_GPL(xadc_parse_dt, "IIO_XADC");
> 
> This function is only used once. Would be better to just move
> it to the file that uses it instead of making a public function.
> 
OK, maybe it is used in another file in a later patch. The commit
message here should explain that.

[PATCH v3 5/6] iio: adc: xilinx-xadc: Add I2C interface support

[Dileep Kumar Nagavarapu]

Add I2C interface support for Xilinx System Management Wizard IP along
with the existing AXI memory-mapped interface. This support enables
monitoring the voltage and temperature on UltraScale+ devices where the
System Management Wizard is connected via I2C.

Key changes:
- Implement 32-bit DRP(Dynamic Reconfiguration Port) packet format as per
  Xilinx PG185 specification.
- Add separate I2C probe with xadc_i2c_of_match_table to handle same
  compatible string("xlnx,system-management-wiz-1.3") on I2C bus.
- Implement delayed version of hardware initialization for I2C interface
  to handle the case where System Management Wizard IP is not ready during
  the I2C probe.
- Add NULL checks for get_dclk_rate callback function in sampling rate
  functions to support interfaces without clock control
- Create separate iio_info structure(xadc_i2c_info) without event
  callbacks for I2C devices
- Add xadc_i2c_transaction() function to handle I2C read/write operations
- Add XADC_TYPE_US_I2C type to distinguish I2C interface from AXI
- Defer XADC hardware initialization until first device access.
- The I2C path reaches the PL SysMon indirectly through a platform
  controller DRP bridge, which may not be operational when the driver
  probes.
- Initialize hardware on first read/write instead of probe() to avoid
  failures caused by temporary unavailability of the downstream path.

Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
---
 drivers/iio/adc/Kconfig            |  15 ++
 drivers/iio/adc/Makefile           |   1 +
 drivers/iio/adc/xilinx-xadc-core.c |  25 +++-
 drivers/iio/adc/xilinx-xadc-i2c.c  | 228 +++++++++++++++++++++++++++++
 drivers/iio/adc/xilinx-xadc.h      |   1 +
 5 files changed, 266 insertions(+), 4 deletions(-)
 create mode 100644 drivers/iio/adc/xilinx-xadc-i2c.c

diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 15ecf001b3ce..9f7f0abdb29e 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -2051,6 +2051,21 @@ config XILINX_XADC
 	  The driver can also be build as a module. If so, the module will be called
 	  xilinx-xadc.
 
+config XILINX_XADC_I2C
+	tristate "Xilinx System Management Wizard I2C Interface support"
+	depends on I2C
+	select XILINX_XADC_CORE
+	help
+	  Say yes here to allow accessing the System Management
+	  Wizard on UltraScale+ devices via I2C.
+
+	  This provides voltage and temperature monitoring capabilities
+	  through the same IIO sysfs interface, but using I2C communication
+	  protocol.
+
+	  The driver can also be build as a module. If so, the module
+	  will be called xilinx-xadc-i2c.
+
 config XILINX_AMS
 	tristate "Xilinx AMS driver"
 	depends on ARCH_ZYNQMP || COMPILE_TEST
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 4cb06243966c..1f22f8a4b439 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -178,3 +178,4 @@ obj-$(CONFIG_XILINX_AMS) += xilinx-ams.o
 xilinx-xadc-common-y := xilinx-xadc-core.o xilinx-xadc-events.o
 obj-$(CONFIG_XILINX_XADC_CORE) += xilinx-xadc-common.o
 obj-$(CONFIG_XILINX_XADC) += xilinx-xadc-platform.o
+obj-$(CONFIG_XILINX_XADC_I2C) += xilinx-xadc-i2c.o
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index d39ff54439ba..1f1a1d5d23d3 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -224,7 +224,7 @@ static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
 	 * non-existing ADC-B powers down the main ADC, so just return and don't
 	 * do anything.
 	 */
-	if (xadc->ops->type == XADC_TYPE_US)
+	if (xadc->ops->type == XADC_TYPE_US || xadc->ops->type == XADC_TYPE_US_I2C)
 		return 0;
 
 	/* Powerdown the ADC-B when it is not needed. */
@@ -246,7 +246,7 @@ static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
 	unsigned int aux_scan_mode = scan_mode >> 16;
 
 	/* UltraScale has only one ADC and supports only continuous mode */
-	if (xadc->ops->type == XADC_TYPE_US)
+	if (xadc->ops->type == XADC_TYPE_US || xadc->ops->type == XADC_TYPE_US_I2C)
 		return XADC_CONF1_SEQ_CONTINUOUS;
 
 	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
@@ -351,6 +351,9 @@ int xadc_read_samplerate(struct xadc *xadc)
 	u16 val16;
 	int ret;
 
+	if (!xadc->ops->get_dclk_rate)
+		return -EOPNOTSUPP;
+
 	ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
 	if (ret)
 		return ret;
@@ -460,9 +463,13 @@ EXPORT_SYMBOL_NS_GPL(xadc_setup_buffer_and_triggers, "IIO_XADC");
 
 int xadc_write_samplerate(struct xadc *xadc, int val)
 {
-	unsigned long clk_rate = xadc_get_dclk_rate(xadc);
+	unsigned long clk_rate;
 	unsigned int div;
 
+	if (!xadc->ops->get_dclk_rate)
+		return -EOPNOTSUPP;
+
+	clk_rate = xadc->ops->get_dclk_rate(xadc);
 	if (!clk_rate)
 		return -EINVAL;
 
@@ -656,6 +663,11 @@ static const struct iio_info xadc_info = {
 	.update_scan_mode = &xadc_update_scan_mode,
 };
 
+static const struct iio_info xadc_i2c_info = {
+	.read_raw = &xadc_read_raw,
+	.write_raw = &xadc_write_raw,
+};
+
 int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
 {
 	struct device *dev = indio_dev->dev.parent;
@@ -767,6 +779,7 @@ EXPORT_SYMBOL_NS_GPL(xadc_parse_dt, "IIO_XADC");
 static const char *const xadc_type_names[] = {
 	[XADC_TYPE_S7] = "xadc",
 	[XADC_TYPE_US] = "xilinx-system-monitor",
+	[XADC_TYPE_US_I2C] = "xilinx-system-monitor",
 };
 
 struct iio_dev *xadc_device_setup(struct device *dev, int size, const struct xadc_ops **ops)
@@ -780,7 +793,11 @@ struct iio_dev *xadc_device_setup(struct device *dev, int size, const struct xad
 		return ERR_PTR(-ENOMEM);
 
 	indio_dev->name = xadc_type_names[(*ops)->type];
-	indio_dev->info = &xadc_info;
+	if ((*ops)->type == XADC_TYPE_US_I2C)
+		indio_dev->info = &xadc_i2c_info;
+	else
+		indio_dev->info = &xadc_info;
+
 	indio_dev->modes = INDIO_DIRECT_MODE;
 
 	return indio_dev;
diff --git a/drivers/iio/adc/xilinx-xadc-i2c.c b/drivers/iio/adc/xilinx-xadc-i2c.c
new file mode 100644
index 000000000000..5628340d7ed5
--- /dev/null
+++ b/drivers/iio/adc/xilinx-xadc-i2c.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx XADC I2C Interface Driver
+ *
+ * Copyright (C) 2026 Advanced Micro Devices, Inc.
+ *
+ * This driver implements I2C interface support for Xilinx System Management
+ * Wizard IP on UltraScale+ devices. It uses the 32-bit DRP (Dynamic
+ * Reconfiguration Port) packet format as per Xilinx PG185 specification.
+ */
+
+#include <linux/bits.h>
+#include <linux/bitfield.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+
+#include <linux/iio/iio.h>
+
+#include "xilinx-xadc.h"
+
+#define XADC_I2C_READ_DATA_SIZE		2
+#define XADC_I2C_WRITE_DATA_SIZE	4	/* 32-bit DRP packet */
+#define XADC_I2C_INSTR_READ		BIT(2)
+#define XADC_I2C_INSTR_WRITE		BIT(3)
+
+#define XADC_I2C_DRP_DATA0_MASK		GENMASK(7, 0)
+#define XADC_I2C_DRP_DATA1_MASK		GENMASK(15, 8)
+#define XADC_I2C_DRP_ADDR_MASK		GENMASK(7, 0)
+
+#define XADC_INPUT_MODE_BITS		16
+
+struct xadc_i2c {
+	struct xadc xadc;
+	struct i2c_client *client;
+	bool hw_initialized;
+	unsigned int conf0;
+	unsigned int bipolar_mask;
+};
+
+static int xadc_i2c_read_transaction(struct xadc *xadc, unsigned int reg, u16 *val)
+{
+	struct xadc_i2c *xadc_i2c = container_of(xadc, struct xadc_i2c, xadc);
+	char write_buffer[XADC_I2C_WRITE_DATA_SIZE] = { 0 };
+	struct i2c_client *client = xadc_i2c->client;
+	char read_buffer[XADC_I2C_READ_DATA_SIZE];
+	int ret;
+
+	write_buffer[2] = FIELD_GET(XADC_I2C_DRP_ADDR_MASK, reg);
+	write_buffer[3] = XADC_I2C_INSTR_READ;
+
+	ret = i2c_master_send(client, write_buffer, XADC_I2C_WRITE_DATA_SIZE);
+	if (ret < 0)
+		return ret;
+
+	ret = i2c_master_recv(client, read_buffer, XADC_I2C_READ_DATA_SIZE);
+	if (ret < 0)
+		return ret;
+
+	*val = FIELD_PREP(XADC_I2C_DRP_DATA0_MASK, read_buffer[0]) |
+	       FIELD_PREP(XADC_I2C_DRP_DATA1_MASK, read_buffer[1]);
+
+	return 0;
+}
+
+static int xadc_i2c_write_transaction(struct xadc *xadc, unsigned int reg, u16 val)
+{
+	struct xadc_i2c *xadc_i2c = container_of(xadc, struct xadc_i2c, xadc);
+	struct i2c_client *client = xadc_i2c->client;
+	char write_buffer[XADC_I2C_WRITE_DATA_SIZE];
+	int ret;
+
+	/* low byte of the 16-bit DRP data value */
+	write_buffer[0] = FIELD_GET(XADC_I2C_DRP_DATA0_MASK, val);
+	/* high byte of the 16-bit DRP data value */
+	write_buffer[1] = FIELD_GET(XADC_I2C_DRP_DATA1_MASK, val);
+	write_buffer[2] = FIELD_GET(XADC_I2C_DRP_ADDR_MASK, reg);
+	write_buffer[3] = XADC_I2C_INSTR_WRITE;
+
+	ret = i2c_master_send(client, write_buffer, XADC_I2C_WRITE_DATA_SIZE);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int xadc_hardware_init(struct xadc *xadc)
+{
+	struct xadc_i2c *xadc_i2c = container_of(xadc, struct xadc_i2c, xadc);
+	int ret;
+
+	for (unsigned int i = 0; i < ARRAY_SIZE(xadc->threshold); i++) {
+		ret = xadc_i2c_read_transaction(xadc, XADC_REG_THRESHOLD(i), &xadc->threshold[i]);
+		if (ret)
+			return ret;
+	}
+
+	ret = xadc_i2c_write_transaction(xadc, XADC_REG_CONF0, xadc_i2c->conf0);
+	if (ret)
+		return ret;
+
+	ret = xadc_i2c_write_transaction(xadc, XADC_REG_INPUT_MODE(0), xadc_i2c->bipolar_mask);
+	if (ret)
+		return ret;
+
+	ret = xadc_i2c_write_transaction(xadc, XADC_REG_INPUT_MODE(1),
+					 xadc_i2c->bipolar_mask >> XADC_INPUT_MODE_BITS);
+	if (ret)
+		return ret;
+
+	xadc_i2c->hw_initialized = true;
+
+	return 0;
+}
+
+static int xadc_i2c_read_reg(struct xadc *xadc, unsigned int reg, u16 *val)
+{
+	struct xadc_i2c *xadc_i2c = container_of(xadc, struct xadc_i2c, xadc);
+
+	/*
+	 * Deferring initialization to the first real read/write means it
+	 * only runs once the device is actually being used, at which point
+	 * the full path down to the PL SysMon is expected to be up. This
+	 * avoids spurious probe failures caused by transient unavailability
+	 * of hardware outside this driver's control.
+	 */
+	if (!xadc_i2c->hw_initialized) {
+		int ret;
+
+		ret = xadc_hardware_init(xadc);
+		if (ret)
+			return ret;
+	}
+
+	return xadc_i2c_read_transaction(xadc, reg, val);
+}
+
+static int xadc_i2c_write_reg(struct xadc *xadc, unsigned int reg, u16 val)
+{
+	struct xadc_i2c *xadc_i2c = container_of(xadc, struct xadc_i2c, xadc);
+
+	/*
+	 * Deferring initialization to the first real read/write means it
+	 * only runs once the device is actually being used, at which point
+	 * the full path down to the PL SysMon is expected to be up. This
+	 * avoids spurious probe failures caused by transient unavailability
+	 * of hardware outside this driver's control.
+	 */
+	if (!xadc_i2c->hw_initialized) {
+		int ret;
+
+		ret = xadc_hardware_init(xadc);
+		if (ret)
+			return ret;
+	}
+
+	return xadc_i2c_write_transaction(xadc, reg, val);
+}
+
+static const struct xadc_ops xadc_system_mgmt_wiz_i2c_ops = {
+	.read = xadc_i2c_read_reg,
+	.write = xadc_i2c_write_reg,
+	.setup_channels = xadc_parse_dt,
+	.type = XADC_TYPE_US_I2C,
+	.temp_scale = 509314,
+	.temp_offset = 280231,
+};
+
+static int xadc_i2c_probe(struct i2c_client *client)
+{
+	struct device *dev = &client->dev;
+	unsigned int conf0, bipolar_mask;
+	const struct xadc_ops *ops;
+	struct iio_dev *indio_dev;
+	struct xadc_i2c *xadc_i2c;
+	struct xadc *xadc;
+	int ret;
+
+	indio_dev = xadc_device_setup(dev, sizeof(*xadc_i2c), &ops);
+	if (IS_ERR(indio_dev))
+		return PTR_ERR(indio_dev);
+
+	xadc_i2c = iio_priv(indio_dev);
+	xadc_i2c->client = client;
+	xadc = &xadc_i2c->xadc;
+	xadc->clk = NULL;
+	xadc->ops = ops;
+
+	ret = devm_mutex_init(xadc->mutex);
+	if (ret)
+		return ret;
+
+	spin_lock_init(&xadc->lock);
+
+	ret = xadc_device_configure(dev, indio_dev, 0, &conf0, &bipolar_mask);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to setup the device\n");
+
+	xadc_i2c->conf0 = conf0;
+	xadc_i2c->bipolar_mask = bipolar_mask;
+	xadc_i2c->hw_initialized = false;
+
+	return devm_iio_device_register(dev, indio_dev);
+}
+
+static const struct of_device_id xadc_i2c_of_match_table[] = {
+	{
+		.compatible = "xlnx,system-management-wiz-1.3",
+		.data = &xadc_system_mgmt_wiz_i2c_ops,
+	},
+	{}
+};
+MODULE_DEVICE_TABLE(of, xadc_i2c_of_match_table);
+
+static struct i2c_driver xadc_i2c_driver = {
+	.probe = xadc_i2c_probe,
+	.driver = {
+		.name = "xadc-i2c",
+		.of_match_table = xadc_i2c_of_match_table,
+	},
+};
+module_i2c_driver(xadc_i2c_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>");
+MODULE_DESCRIPTION("Xilinx XADC I2C Interface Driver");
diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h
index 67efa093157e..178d4fa0b249 100644
--- a/drivers/iio/adc/xilinx-xadc.h
+++ b/drivers/iio/adc/xilinx-xadc.h
@@ -69,6 +69,7 @@ struct xadc {
 enum xadc_type {
 	XADC_TYPE_S7, /* Series 7 */
 	XADC_TYPE_US, /* UltraScale and UltraScale+ */
+	XADC_TYPE_US_I2C, /* UltraScale+ I2C interface */
 };
 
 struct xadc_ops {
-- 
2.34.1

[PATCH v3 6/6] iio: adc: xilinx-xadc: Correct Write edge in CFG

[Dileep Kumar Nagavarapu]

UG585 states about the PS-XADC interface configuration steps,
REDGE is 1 and WEDGE is 0, this is consistent with the XADCIF_CFG
register default value.

Current driver set WEDGE which is inconsistent with TRM, this patch
fix the WEDGE parameter setting.

Signed-off-by: Conall O'Griofa <conall.ogriofa@amd.com>
Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
---
 drivers/iio/adc/xilinx-xadc-platform.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/xilinx-xadc-platform.c b/drivers/iio/adc/xilinx-xadc-platform.c
index bd033315c72f..b113f904b8fa 100644
--- a/drivers/iio/adc/xilinx-xadc-platform.c
+++ b/drivers/iio/adc/xilinx-xadc-platform.c
@@ -346,7 +346,7 @@ static int xadc_zynq_setup(struct platform_device *pdev, struct iio_dev *indio_d
 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE | XADC_ZYNQ_CFG_REDGE |
-			       XADC_ZYNQ_CFG_WEDGE | tck_div | XADC_ZYNQ_CFG_IGAP(igap));
+			       tck_div | XADC_ZYNQ_CFG_IGAP(igap));
 
 	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX_HZ) {
 		ret = clk_set_rate(xadc->clk, pcap_rate);
-- 
2.34.1

Re: [PATCH v3 6/6] iio: adc: xilinx-xadc: Correct Write edge in CFG

[David Lechner]

On 7/29/26 7:54 AM, Dileep Kumar Nagavarapu wrote:
> UG585 states about the PS-XADC interface configuration steps,
> REDGE is 1 and WEDGE is 0, this is consistent with the XADCIF_CFG
> register default value.
> 
> Current driver set WEDGE which is inconsistent with TRM, this patch
> fix the WEDGE parameter setting.
> 
> Signed-off-by: Conall O'Griofa <conall.ogriofa@amd.com>
> Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
> ---
>  drivers/iio/adc/xilinx-xadc-platform.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/adc/xilinx-xadc-platform.c b/drivers/iio/adc/xilinx-xadc-platform.c
> index bd033315c72f..b113f904b8fa 100644
> --- a/drivers/iio/adc/xilinx-xadc-platform.c
> +++ b/drivers/iio/adc/xilinx-xadc-platform.c
> @@ -346,7 +346,7 @@ static int xadc_zynq_setup(struct platform_device *pdev, struct iio_dev *indio_d
>  	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
>  	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
>  	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE | XADC_ZYNQ_CFG_REDGE |
> -			       XADC_ZYNQ_CFG_WEDGE | tck_div | XADC_ZYNQ_CFG_IGAP(igap));
> +			       tck_div | XADC_ZYNQ_CFG_IGAP(igap));
>  
>  	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX_HZ) {
>  		ret = clk_set_rate(xadc->clk, pcap_rate);

This sounds like a fix, so should have Fixes: tag and be the first
patch in the series.

Also would be good to know if this is causing actual problems or
not so we know if it needs to be backported or not.