[PATCH v2] iio: accel: adxl372: replace manual bitfield ops with FIELD_GET()

[PATCH v2] iio: accel: adxl372: replace manual bitfield ops with FIELD_GET()

[Caio Groff]

From: Caio Groff <caio.groff@usp.br>

v2: add missing blank line after reg_val_l assignment

Replace manual bit shifting and masking with FIELD_GET()
macros for clarity and consistency with kernel coding style.

Signed-off-by: Caio Groff <caio.groff@usp.br>
---
 drivers/iio/accel/adxl372.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/accel/adxl372.c b/drivers/iio/accel/adxl372.c
index e375d068a3f5..daf5813ff50e 100644
--- a/drivers/iio/accel/adxl372.c
+++ b/drivers/iio/accel/adxl372.c
@@ -150,6 +150,11 @@
 #define ADXL372_Y_AXIS_EN(x)			((x) & BIT(1))
 #define ADXL372_Z_AXIS_EN(x)			((x) & BIT(2))
 
+/* ADXL372_TIME_INACT */
+#define ADXL372_TIME_INACT_MASK_H  GENMASK(15, 8)
+#define ADXL372_TIME_INACT_MASK_L  GENMASK(7, 0)
+
+
 /*
  * At +/- 200g with 12-bit resolution, scale is computed as:
  * (200 + 200) * 9.81 / (2^12 - 1) = 0.958241
@@ -577,8 +582,8 @@ static int adxl372_set_inactivity_time_ms(struct adxl372_state *st,
 		scale_factor = st->chip_info->inact_time_scale_low_ms;
 
 	res = DIV_ROUND_CLOSEST(inact_time_ms, scale_factor);
-	reg_val_h = (res >> 8) & 0xFF;
-	reg_val_l = res & 0xFF;
+	reg_val_h = FIELD_GET(ADXL372_TIME_INACT_MASK_H, res);
+	reg_val_l = FIELD_GET(ADXL372_TIME_INACT_MASK_L, res);
 
 	ret = regmap_write(st->regmap, ADXL372_TIME_INACT_H, reg_val_h);
 	if (ret < 0)
-- 
2.53.0

Re: [PATCH v2] iio: accel: adxl372: replace manual bitfield ops with FIELD_GET()

[Maxwell Doose]

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Hi Caio,

On Tue Jul 7, 2026 at 10:06 PM CDT
Caio Groff <caio.groff@usp.br> wrote:

> From: Caio Groff <caio.groff@usp.br>
>
> v2: add missing blank line after reg_val_l assignment
>
> Replace manual bit shifting and masking with FIELD_GET()
> macros for clarity and consistency with kernel coding style.
>
> Signed-off-by: Caio Groff <caio.groff@usp.br>
> ---
>  drivers/iio/accel/adxl372.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iio/accel/adxl372.c b/drivers/iio/accel/adxl372.c
> index e375d068a3f5..daf5813ff50e 100644
> --- a/drivers/iio/accel/adxl372.c
> +++ b/drivers/iio/accel/adxl372.c
> @@ -150,6 +150,11 @@
>  #define ADXL372_Y_AXIS_EN(x)			((x) & BIT(1))
>  #define ADXL372_Z_AXIS_EN(x)			((x) & BIT(2))
>  
> +/* ADXL372_TIME_INACT */
> +#define ADXL372_TIME_INACT_MASK_H  GENMASK(15, 8)
> +#define ADXL372_TIME_INACT_MASK_L  GENMASK(7, 0)
> +
> +
>  /*
>   * At +/- 200g with 12-bit resolution, scale is computed as:
>   * (200 + 200) * 9.81 / (2^12 - 1) = 0.958241
> @@ -577,8 +582,8 @@ static int adxl372_set_inactivity_time_ms(struct adxl372_state *st,
>  		scale_factor = st->chip_info->inact_time_scale_low_ms;
>  
>  	res = DIV_ROUND_CLOSEST(inact_time_ms, scale_factor);
> -	reg_val_h = (res >> 8) & 0xFF;
> -	reg_val_l = res & 0xFF;
> +	reg_val_h = FIELD_GET(ADXL372_TIME_INACT_MASK_H, res);
> +	reg_val_l = FIELD_GET(ADXL372_TIME_INACT_MASK_L, res);
>  
>  	ret = regmap_write(st->regmap, ADXL372_TIME_INACT_H, reg_val_h);
>  	if (ret < 0)

First things first, don't resubmit for minor style issues. Most of the
time these are fixed while applying. Secondly, don't submit a new
version until at least 24 hours have passed, this gives enough time for
more people to review.

Also, put the changelog for new versions underneath the --- so it isn't
included in the commit.

Last thing, don't forget to carry through any tags for new versions
where there was very little or no change from the previous version
(though some people may do it differently).


-- 
best regards,
max


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Re: [PATCH v2] iio: accel: adxl372: replace manual bitfield ops with FIELD_GET()

[Andy Shevchenko]

On Wed, Jul 08, 2026 at 12:06:11AM -0300, Caio Groff wrote:

> v2: add missing blank line after reg_val_l assignment
> 
> Replace manual bit shifting and masking with FIELD_GET()
> macros for clarity and consistency with kernel coding style.

All what Maxwell said plus the same comments as per v1 by me.

-- 
With Best Regards,
Andy Shevchenko