Re: [PATCH 3/9] dmaengine: dw-axi-dmac: Use bus width capability helpers

[Frank Li <Frank.li@oss.nxp.com>]

On Thu, Jul 30, 2026 at 03:23:10PM +0100, Nuno Sá via B4 Relay wrote:
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>
> From: Nuno Sá <nuno.sa@analog.com>
>
> Advertise the supported bus widths through dma_set_src_bus_widths()
> and dma_set_dst_bus_widths() instead of assigning the legacy u32 masks
> directly. This keeps the driver using the new bitmap representation
> while preserving legacy fields during the transition.
>
> Signed-off-by: Nuno Sá <nuno.sa@analog.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 39 +++++++++++++++-----------
>  1 file changed, 23 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index bcefaff03b5c..69cac7e3625f 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -33,20 +33,6 @@
>  #include "../dmaengine.h"
>  #include "../virt-dma.h"
>
> -/*
> - * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
> - * master data bus width up to 512 bits (for both AXI master interfaces), but
> - * it depends on IP block configuration.
> - */
> -#define AXI_DMA_BUSWIDTHS                \
> -       (DMA_SLAVE_BUSWIDTH_1_BYTE      | \
> -       DMA_SLAVE_BUSWIDTH_2_BYTES      | \
> -       DMA_SLAVE_BUSWIDTH_4_BYTES      | \
> -       DMA_SLAVE_BUSWIDTH_8_BYTES      | \
> -       DMA_SLAVE_BUSWIDTH_16_BYTES     | \
> -       DMA_SLAVE_BUSWIDTH_32_BYTES     | \
> -       DMA_SLAVE_BUSWIDTH_64_BYTES)
> -
>  #define AXI_DMA_FLAG_HAS_APB_REGS      BIT(0)
>  #define AXI_DMA_FLAG_HAS_RESETS                BIT(1)
>  #define AXI_DMA_FLAG_USE_CFG2          BIT(2)
> @@ -1482,6 +1468,20 @@ static int dw_probe(struct platform_device *pdev)
>         unsigned int flags;
>         u32 i;
>         int ret;
> +       /*
> +        * The set of bus widths supported by the DMA controller. DW AXI DMAC
> +        * supports master data bus width up to 512 bits (for both AXI master
> +        * interfaces), but it depends on IP block configuration.
> +        */
> +       enum dma_slave_buswidth axi_dma_buswidths[] = {
> +               DMA_SLAVE_BUSWIDTH_1_BYTE,
> +               DMA_SLAVE_BUSWIDTH_2_BYTES,
> +               DMA_SLAVE_BUSWIDTH_4_BYTES,
> +               DMA_SLAVE_BUSWIDTH_8_BYTES,
> +               DMA_SLAVE_BUSWIDTH_16_BYTES,
> +               DMA_SLAVE_BUSWIDTH_32_BYTES,
> +               DMA_SLAVE_BUSWIDTH_64_BYTES,
> +       };
>
>         chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
>         if (!chip)
> @@ -1565,8 +1565,15 @@ static int dw_probe(struct platform_device *pdev)
>
>         /* DMA capabilities */
>         dw->dma.max_burst = hdata->axi_rw_burst_len;
> -       dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS;
> -       dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
> +       ret = dma_set_src_bus_widths(&dw->dma, axi_dma_buswidths,
> +                                    ARRAY_SIZE(axi_dma_buswidths));
> +       if (ret)
> +               return ret;
> +
> +       ret = dma_set_dst_bus_widths(&dw->dma, axi_dma_buswidths,
> +                                    ARRAY_SIZE(axi_dma_buswidths));
> +       if (ret)
> +               return ret;
>         dw->dma.directions = BIT(DMA_MEM_TO_MEM);
>         dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
>         dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
>
> --
> 2.55.0
>
>