Re: [GIT PULL] Intel IOMMU for 4.1

[Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>]

On Sun, 2015-04-26 at 09:51 +0100, David Woodhouse wrote:
> Linus,
> 
> Please pull the following changes (since v3.19) from
> 
>         git://git.infradead.org/intel-iommu.git
> 
> This lays a little of the groundwork for upcoming Shared Virtual
> Memory support — fixing some bogus #defines for capability bits and
> adding the new ones, and starting to use the new wider page tables
> where we can, in anticipation of actually filling in the new fields
> therein.
> 
> It also allows graphics devices to be assigned to VM guests again.
> This got broken in 3.17 by disallowing assignment of RMRR-afflicted
> devices. Like USB, we do understand why there's an RMRR for graphics
> devices — and unlike USB, it's actually sane. So we can make an
> exception for graphics devices, just as we do USB controllers.
> 
> Finally, tone down the warning about the X2APIC_OPT_OUT bit, due to
> persistent requests. X2APIC_OPT_OUT was added to the spec as a nasty
> hack to allow broken BIOSes to forbid us from using X2APIC when they
> do stupid and invasive things and would break if we did.
> 
> Someone noticed that since Windows doesn't have full IOMMU support for
> DMA protection, setting the X2APIC_OPT_OUT bit made Windows avoid
> initialising the IOMMU on the graphics unit altogether.
> 
> This means that it would be available for use in "driver mode", where
> the IOMMU registers are made available through a BAR of the graphics
> device and the graphics driver can do SVM all for itself.
> 
> So they started setting the X2APIC_OPT_OUT bit on *all* platforms with
> SVM capabilities. And even the platforms which *might*, if the planets
> had been aligned correctly, possibly have had SVM capability but which
> in practice actually don't.
> 
> 
> David Woodhouse (4):
>       iommu/vt-d: kill bogus ecap_niotlb_iunits()
>       iommu/vt-d: Allow RMRR on graphics devices too

Curious why these weren't posted to the mailing list.  This one in
particular not only ignores RMRR on IGD, but any PCI class display
device.  We may understand why IGD has RMRRs, but we certainly don't
understand enough to ignore RMRRs for other GPUs, should they exist.
Thanks,

Alex

>       iommu/vt-d: Add new extended capabilities from v2.3 VT-d specification
>       iommu/vt-d: support extended root and context entries
> 
> Fenghua Yu (1):
>       iommu/vt-d: Print x2apic opt out info instead of printing a warning
> 
>  drivers/iommu/intel-iommu.c         | 142 +++++++++++++++++-------------------
>  drivers/iommu/intel_irq_remapping.c |   5 +-
>  include/linux/intel-iommu.h         |  18 ++++-
>  3 files changed, 82 insertions(+), 83 deletions(-)
> 
> 
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