[PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Tirumalesh Chalamarla]

Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
namespaces; specifically within a given node SMMU0 and SMMU1 share,
as does SMMU2 and SMMU3.

This patch make sures ASID and VMID space is unique across cavium SMMUv2.

changes from V3:
	- Removed redundent variable.

changes from V2:
	- removed *_base from DT, and replaced with compatible string

changes from V1:
	- rebased on top of 16 bit VMID patch
	- removed redundent options from DT
	- insted of transform, DT now supplies starting ASID/VMID

Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
Signed-off-by: Akula Geethasowjanya <Geethasowjanya.Akula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
---
 Documentation/arm64/silicon-errata.txt             |  1 +
 .../devicetree/bindings/iommu/arm,smmu.txt         |  1 +
 drivers/iommu/arm-smmu.c                           | 43 ++++++++++++++++------
 3 files changed, 34 insertions(+), 11 deletions(-)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 58b71dd..3747a4b 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -56,3 +56,4 @@ stable kernels.
 |                |                 |                 |                         |
 | Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
+| Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 7180745..19fe6f2 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -16,6 +16,7 @@ conditions.
                         "arm,mmu-400"
                         "arm,mmu-401"
                         "arm,mmu-500"
+                        "cavium,smmu-v2"

                   depending on the particular implementation and/or the
                   version of the architecture implemented.
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 247a469..bfe38f3 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -326,6 +326,11 @@ struct arm_smmu_device {

 	struct list_head		list;
 	struct rb_root			masters;
+	/*
+	 *The following fields are specific to Cavium, Thunder
+	 */
+	u32				cavium_id_base;
+
 };

 struct arm_smmu_cfg {
@@ -335,8 +340,8 @@ struct arm_smmu_cfg {
 };
 #define INVALID_IRPTNDX			0xff

-#define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)
-#define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)
+#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
+#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)

 enum arm_smmu_domain_stage {
 	ARM_SMMU_DOMAIN_S1 = 0,
@@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
 	const char *prop;
 };

+static u32 cavium_smmu_context_count;
+
 static struct arm_smmu_option_prop arm_smmu_options[] = {
 	{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 	{ 0, NULL},
@@ -575,11 +582,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)

 	if (stage1) {
 		base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
-		writel_relaxed(ARM_SMMU_CB_ASID(cfg),
+		writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg),
 			       base + ARM_SMMU_CB_S1_TLBIASID);
 	} else {
 		base = ARM_SMMU_GR0(smmu);
-		writel_relaxed(ARM_SMMU_CB_VMID(cfg),
+		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg),
 			       base + ARM_SMMU_GR0_TLBIVMID);
 	}

@@ -601,7 +608,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,

 		if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
 			iova &= ~12UL;
-			iova |= ARM_SMMU_CB_ASID(cfg);
+			iova |= ARM_SMMU_CB_ASID(smmu, cfg);
 			do {
 				writel_relaxed(iova, reg);
 				iova += granule;
@@ -609,7 +616,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
 #ifdef CONFIG_64BIT
 		} else {
 			iova >>= 12;
-			iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
+			iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48;
 			do {
 				writeq_relaxed(iova, reg);
 				iova += granule >> 12;
@@ -629,7 +636,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
 #endif
 	} else {
 		reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
-		writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
+		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg);
 	}
 }

@@ -738,7 +745,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 #endif
 		/* if 16bit VMID supported set VMID in CBA2R */
 		if (smmu->features & ARM_SMMU_FEAT_VMID16)
-			reg |= ARM_SMMU_CB_VMID(cfg) << CBA2R_VMID_SHIFT;
+			reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT;

 		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
 	}
@@ -757,7 +764,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 			(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 	} else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
 		/*16 bit VMID is not supported set 8 bit VMID here */
-		reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
+		reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT;
 	}
 	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));

@@ -765,11 +772,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 	if (stage1) {
 		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

-		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
+		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);

 		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
-		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
+		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1);
 	} else {
 		reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
@@ -1717,6 +1724,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
 	{ .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
 	{ .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
 	{ .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
+	{ .compatible = "cavium,smmu-v2", .data = (void *)ARM_SMMU_V2 },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
@@ -1829,6 +1837,19 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)

 	INIT_LIST_HEAD(&smmu->list);
 	spin_lock(&arm_smmu_devices_lock);
+
+	/*
+	 * Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
+	 * namespaces; specifically within a given node SMMU0 and SMMU1 share,
+	 * as does SMMU2 and SMMU3. see if this is a Cavium SMMU, if so
+	 * set asid and vmid base such that each SMMU gets unique
+	 * asid/vmid space.
+	 */
+	if (of_device_is_compatible(dev->of_node, "cavium,smmu-v2")) {
+		smmu->cavium_id_base = cavium_smmu_context_count;
+		cavium_smmu_context_count += smmu->num_context_banks;
+	}
+
 	list_add(&smmu->list, &arm_smmu_devices);
 	spin_unlock(&arm_smmu_devices_lock);

--
2.1.0

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Will Deacon]

On Thu, Mar 03, 2016 at 07:44:03PM -0800, Tirumalesh Chalamarla wrote:
> Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
> namespaces; specifically within a given node SMMU0 and SMMU1 share,
> as does SMMU2 and SMMU3.
> 
> This patch make sures ASID and VMID space is unique across cavium SMMUv2.
> 
> changes from V3:
> 	- Removed redundent variable.

[...]

> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index 247a469..bfe38f3 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -326,6 +326,11 @@ struct arm_smmu_device {
> 
>  	struct list_head		list;
>  	struct rb_root			masters;
> +	/*
> +	 *The following fields are specific to Cavium, Thunder
> +	 */
> +	u32				cavium_id_base;
> +
>  };
> 
>  struct arm_smmu_cfg {
> @@ -335,8 +340,8 @@ struct arm_smmu_cfg {
>  };
>  #define INVALID_IRPTNDX			0xff
> 
> -#define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)
> -#define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)
> +#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
> +#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)
> 
>  enum arm_smmu_domain_stage {
>  	ARM_SMMU_DOMAIN_S1 = 0,
> @@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
>  	const char *prop;
>  };
> 
> +static u32 cavium_smmu_context_count;

I thought you were going to make this an atomic_t?

Will

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Tirumalesh Chalamarla]

On 03/04/2016 08:02 AM, Will Deacon wrote:
> On Thu, Mar 03, 2016 at 07:44:03PM -0800, Tirumalesh Chalamarla wrote:
>> Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
>> namespaces; specifically within a given node SMMU0 and SMMU1 share,
>> as does SMMU2 and SMMU3.
>>
>> This patch make sures ASID and VMID space is unique across cavium SMMUv2.
>>
>> changes from V3:
>> 	- Removed redundent variable.
>
> [...]
>
>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>> index 247a469..bfe38f3 100644
>> --- a/drivers/iommu/arm-smmu.c
>> +++ b/drivers/iommu/arm-smmu.c
>> @@ -326,6 +326,11 @@ struct arm_smmu_device {
>>
>>   	struct list_head		list;
>>   	struct rb_root			masters;
>> +	/*
>> +	 *The following fields are specific to Cavium, Thunder
>> +	 */
>> +	u32				cavium_id_base;
>> +
>>   };
>>
>>   struct arm_smmu_cfg {
>> @@ -335,8 +340,8 @@ struct arm_smmu_cfg {
>>   };
>>   #define INVALID_IRPTNDX			0xff
>>
>> -#define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)
>> -#define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)
>> +#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
>> +#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)
>>
>>   enum arm_smmu_domain_stage {
>>   	ARM_SMMU_DOMAIN_S1 = 0,
>> @@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
>>   	const char *prop;
>>   };
>>
>> +static u32 cavium_smmu_context_count;
>
> I thought you were going to make this an atomic_t?
well i moved variable handling inside atomic context.
with atomic_t i still needed 2 operations like read and add
it seems atomic_add_return is not sufficient.

in any case i thought why not use the atomic context that is already 
there. if you feel the use of atomic_t is more natural, i will resend 
again.

Thanks,
Tirumalesh.
>
> Will
>

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Tirumalesh Chalamarla]

On 03/04/2016 10:09 AM, Tirumalesh Chalamarla wrote:
>
>
> On 03/04/2016 08:02 AM, Will Deacon wrote:
>> On Thu, Mar 03, 2016 at 07:44:03PM -0800, Tirumalesh Chalamarla wrote:
>>> Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
>>> namespaces; specifically within a given node SMMU0 and SMMU1 share,
>>> as does SMMU2 and SMMU3.
>>>
>>> This patch make sures ASID and VMID space is unique across cavium
>>> SMMUv2.
>>>
>>> changes from V3:
>>>     - Removed redundent variable.
>>
>> [...]
>>
>>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>>> index 247a469..bfe38f3 100644
>>> --- a/drivers/iommu/arm-smmu.c
>>> +++ b/drivers/iommu/arm-smmu.c
>>> @@ -326,6 +326,11 @@ struct arm_smmu_device {
>>>
>>>       struct list_head        list;
>>>       struct rb_root            masters;
>>> +    /*
>>> +     *The following fields are specific to Cavium, Thunder
>>> +     */
>>> +    u32                cavium_id_base;
>>> +
>>>   };
>>>
>>>   struct arm_smmu_cfg {
>>> @@ -335,8 +340,8 @@ struct arm_smmu_cfg {
>>>   };
>>>   #define INVALID_IRPTNDX            0xff
>>>
>>> -#define ARM_SMMU_CB_ASID(cfg)        ((cfg)->cbndx)
>>> -#define ARM_SMMU_CB_VMID(cfg)        ((cfg)->cbndx + 1)
>>> +#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base +
>>> (cfg)->cbndx)
>>> +#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base +
>>> (cfg)->cbndx + 1)
>>>
>>>   enum arm_smmu_domain_stage {
>>>       ARM_SMMU_DOMAIN_S1 = 0,
>>> @@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
>>>       const char *prop;
>>>   };
>>>
>>> +static u32 cavium_smmu_context_count;
>>
>> I thought you were going to make this an atomic_t?
> well i moved variable handling inside atomic context.
> with atomic_t i still needed 2 operations like read and add
> it seems atomic_add_return is not sufficient.
>
ignore this, will send with atomic_t if that feels more natural.
> in any case i thought why not use the atomic context that is already
> there. if you feel the use of atomic_t is more natural, i will resend
> again.
>
> Thanks,
> Tirumalesh.
>>
>> Will
>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Tirumalesh Chalamarla]

Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
namespaces; specifically within a given node SMMU0 and SMMU1 share,
as does SMMU2 and SMMU3.

This patch make sure ASID and VMID space is unique across cavium SMMUv2.

changes from V3:
	- Removed redundent variable.
	- Used atomic_t for maintaining running total

changes from V2:
	- removed *_base from DT, and replaced with compatible string

changes from V1:
	- rebased on top of 16 bit VMID patch
	- removed redundent options from DT
	- insted of transform, DT now supplies starting ASID/VMID

Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
Signed-off-by: Akula Geethasowjanya <Geethasowjanya.Akula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
---
 Documentation/arm64/silicon-errata.txt             |  1 +
 .../devicetree/bindings/iommu/arm,smmu.txt         |  1 +
 drivers/iommu/arm-smmu.c                           | 42 ++++++++++++++++------
 3 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 58b71dd..3747a4b 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -56,3 +56,4 @@ stable kernels.
 |                |                 |                 |                         |
 | Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
+| Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 7180745..19fe6f2 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -16,6 +16,7 @@ conditions.
                         "arm,mmu-400"
                         "arm,mmu-401"
                         "arm,mmu-500"
+                        "cavium,smmu-v2"
 
                   depending on the particular implementation and/or the
                   version of the architecture implemented.
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 247a469..e793b0a 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -326,6 +326,11 @@ struct arm_smmu_device {
 
 	struct list_head		list;
 	struct rb_root			masters;
+	/*
+	 *The following fields are specific to Cavium, Thunder
+	 */
+	u32				cavium_id_base;
+
 };
 
 struct arm_smmu_cfg {
@@ -335,8 +340,8 @@ struct arm_smmu_cfg {
 };
 #define INVALID_IRPTNDX			0xff
 
-#define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)
-#define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)
+#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
+#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)
 
 enum arm_smmu_domain_stage {
 	ARM_SMMU_DOMAIN_S1 = 0,
@@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
 	const char *prop;
 };
 
+static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);
+
 static struct arm_smmu_option_prop arm_smmu_options[] = {
 	{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 	{ 0, NULL},
@@ -575,11 +582,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)
 
 	if (stage1) {
 		base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
-		writel_relaxed(ARM_SMMU_CB_ASID(cfg),
+		writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg),
 			       base + ARM_SMMU_CB_S1_TLBIASID);
 	} else {
 		base = ARM_SMMU_GR0(smmu);
-		writel_relaxed(ARM_SMMU_CB_VMID(cfg),
+		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg),
 			       base + ARM_SMMU_GR0_TLBIVMID);
 	}
 
@@ -601,7 +608,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
 
 		if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
 			iova &= ~12UL;
-			iova |= ARM_SMMU_CB_ASID(cfg);
+			iova |= ARM_SMMU_CB_ASID(smmu, cfg);
 			do {
 				writel_relaxed(iova, reg);
 				iova += granule;
@@ -609,7 +616,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
 #ifdef CONFIG_64BIT
 		} else {
 			iova >>= 12;
-			iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
+			iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48;
 			do {
 				writeq_relaxed(iova, reg);
 				iova += granule >> 12;
@@ -629,7 +636,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
 #endif
 	} else {
 		reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
-		writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
+		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg);
 	}
 }
 
@@ -738,7 +745,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 #endif
 		/* if 16bit VMID supported set VMID in CBA2R */
 		if (smmu->features & ARM_SMMU_FEAT_VMID16)
-			reg |= ARM_SMMU_CB_VMID(cfg) << CBA2R_VMID_SHIFT;
+			reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT;
 
 		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
 	}
@@ -757,7 +764,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 			(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 	} else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
 		/*16 bit VMID is not supported set 8 bit VMID here */
-		reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
+		reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT;
 	}
 	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
 
@@ -765,11 +772,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 	if (stage1) {
 		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
 
-		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
+		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);
 
 		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
-		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
+		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1);
 	} else {
 		reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
@@ -1717,6 +1724,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
 	{ .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
 	{ .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
 	{ .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
+	{ .compatible = "cavium,smmu-v2", .data = (void *)ARM_SMMU_V2 },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
@@ -1826,6 +1834,18 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
 			goto out_free_irqs;
 		}
 	}
+	/*
+	 * Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
+	 * namespaces; specifically within a given node SMMU0 and SMMU1 share,
+	 * as does SMMU2 and SMMU3. see if this is a Cavium SMMU, if so
+	 * set asid and vmid base such that each SMMU gets unique
+	 * asid/vmid space.
+	 */
+	if (of_device_is_compatible(dev->of_node, "cavium,smmu-v2")) {
+		smmu->cavium_id_base = atomic_add_return(smmu->num_context_banks,
+				&cavium_smmu_context_count);
+		smmu->cavium_id_base -= smmu->num_context_banks;
+	}
 
 	INIT_LIST_HEAD(&smmu->list);
 	spin_lock(&arm_smmu_devices_lock);
-- 
2.1.0

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Will Deacon]

On Fri, Mar 04, 2016 at 10:39:44AM -0800, Tirumalesh Chalamarla wrote:
> Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
> namespaces; specifically within a given node SMMU0 and SMMU1 share,
> as does SMMU2 and SMMU3.
> 
> This patch make sure ASID and VMID space is unique across cavium SMMUv2.
> 
> changes from V3:
> 	- Removed redundent variable.
> 	- Used atomic_t for maintaining running total
> 
> changes from V2:
> 	- removed *_base from DT, and replaced with compatible string
> 
> changes from V1:
> 	- rebased on top of 16 bit VMID patch
> 	- removed redundent options from DT
> 	- insted of transform, DT now supplies starting ASID/VMID
> 
> Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
> Signed-off-by: Akula Geethasowjanya <Geethasowjanya.Akula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
> ---
>  Documentation/arm64/silicon-errata.txt             |  1 +
>  .../devicetree/bindings/iommu/arm,smmu.txt         |  1 +
>  drivers/iommu/arm-smmu.c                           | 42 ++++++++++++++++------
>  3 files changed, 33 insertions(+), 11 deletions(-)

Hmm, this doesn't seem to apply to my iommu/devel branch. Am I missing
some dependency?

Will

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Tirumalesh Chalamarla]

On 03/04/2016 12:59 PM, Will Deacon wrote:
> On Fri, Mar 04, 2016 at 10:39:44AM -0800, Tirumalesh Chalamarla wrote:
>> Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
>> namespaces; specifically within a given node SMMU0 and SMMU1 share,
>> as does SMMU2 and SMMU3.
>>
>> This patch make sure ASID and VMID space is unique across cavium SMMUv2.
>>
>> changes from V3:
>> 	- Removed redundent variable.
>> 	- Used atomic_t for maintaining running total
>>
>> changes from V2:
>> 	- removed *_base from DT, and replaced with compatible string
>>
>> changes from V1:
>> 	- rebased on top of 16 bit VMID patch
>> 	- removed redundent options from DT
>> 	- insted of transform, DT now supplies starting ASID/VMID
>>
>> Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
>> Signed-off-by: Akula Geethasowjanya <Geethasowjanya.Akula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
>> ---
>>   Documentation/arm64/silicon-errata.txt             |  1 +
>>   .../devicetree/bindings/iommu/arm,smmu.txt         |  1 +
>>   drivers/iommu/arm-smmu.c                           | 42 ++++++++++++++++------
>>   3 files changed, 33 insertions(+), 11 deletions(-)
>
> Hmm, this doesn't seem to apply to my iommu/devel branch. Am I missing
> some dependency?
>
there should not, i will repost based on that branch.

> Will
>

[PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Tirumalesh Chalamarla]

Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
namespaces; specifically within a given node SMMU0 and SMMU1 share,
as does SMMU2 and SMMU3.

This patch make sure ASID and VMID space is unique across cavium SMMUv2.

changes from V3:
	- Removed redundent variable.
	- Used atomic_t for maintaining running total

changes from V2:
	- removed *_base from DT, and replaced with compatible string

changes from V1:
	- rebased on top of 16 bit VMID patch
	- removed redundent options from DT
	- insted of transform, DT now supplies starting ASID/VMID

Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
Signed-off-by: Akula Geethasowjanya <Geethasowjanya.Akula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
---
 Documentation/arm64/silicon-errata.txt             |  1 +
 .../devicetree/bindings/iommu/arm,smmu.txt         |  1 +
 drivers/iommu/arm-smmu.c                           | 42 ++++++++++++++++------
 3 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 58b71dd..3747a4b 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -56,3 +56,4 @@ stable kernels.
 |                |                 |                 |                         |
 | Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
+| Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 7180745..19fe6f2 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -16,6 +16,7 @@ conditions.
                         "arm,mmu-400"
                         "arm,mmu-401"
                         "arm,mmu-500"
+                        "cavium,smmu-v2"

                   depending on the particular implementation and/or the
                   version of the architecture implemented.
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 247a469..e793b0a 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -326,6 +326,11 @@ struct arm_smmu_device {

 	struct list_head		list;
 	struct rb_root			masters;
+	/*
+	 *The following fields are specific to Cavium, Thunder
+	 */
+	u32				cavium_id_base;
+
 };

 struct arm_smmu_cfg {
@@ -335,8 +340,8 @@ struct arm_smmu_cfg {
 };
 #define INVALID_IRPTNDX			0xff

-#define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)
-#define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)
+#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
+#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)

 enum arm_smmu_domain_stage {
 	ARM_SMMU_DOMAIN_S1 = 0,
@@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
 	const char *prop;
 };

+static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);
+
 static struct arm_smmu_option_prop arm_smmu_options[] = {
 	{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 	{ 0, NULL},
@@ -575,11 +582,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)

 	if (stage1) {
 		base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
-		writel_relaxed(ARM_SMMU_CB_ASID(cfg),
+		writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg),
 			       base + ARM_SMMU_CB_S1_TLBIASID);
 	} else {
 		base = ARM_SMMU_GR0(smmu);
-		writel_relaxed(ARM_SMMU_CB_VMID(cfg),
+		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg),
 			       base + ARM_SMMU_GR0_TLBIVMID);
 	}

@@ -601,7 +608,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,

 		if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
 			iova &= ~12UL;
-			iova |= ARM_SMMU_CB_ASID(cfg);
+			iova |= ARM_SMMU_CB_ASID(smmu, cfg);
 			do {
 				writel_relaxed(iova, reg);
 				iova += granule;
@@ -609,7 +616,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
 #ifdef CONFIG_64BIT
 		} else {
 			iova >>= 12;
-			iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
+			iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48;
 			do {
 				writeq_relaxed(iova, reg);
 				iova += granule >> 12;
@@ -629,7 +636,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
 #endif
 	} else {
 		reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
-		writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
+		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg);
 	}
 }

@@ -738,7 +745,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 #endif
 		/* 16-bit VMIDs live in CBA2R */
 		if (smmu->features & ARM_SMMU_FEAT_VMID16)
-			reg |= ARM_SMMU_CB_VMID(cfg) << CBA2R_VMID_SHIFT;
+			reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT;

 		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
 	}
@@ -757,7 +764,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 			(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 	} else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
 		/* 8-bit VMIDs live in CBAR */
-		reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
+		reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT;
 	}
 	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));

@@ -765,11 +772,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 	if (stage1) {
 		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

-		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
+		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);

 		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
-		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
+		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1);
 	} else {
 		reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
@@ -1717,6 +1724,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
 	{ .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
 	{ .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
 	{ .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
+	{ .compatible = "cavium,smmu-v2", .data = (void *)ARM_SMMU_V2 },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
@@ -1826,6 +1834,18 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
 			goto out_free_irqs;
 		}
 	}
+	/*
+	 * Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
+	 * namespaces; specifically within a given node SMMU0 and SMMU1 share,
+	 * as does SMMU2 and SMMU3. see if this is a Cavium SMMU, if so
+	 * set asid and vmid base such that each SMMU gets unique
+	 * asid/vmid space.
+	 */
+	if (of_device_is_compatible(dev->of_node, "cavium,smmu-v2")) {
+		smmu->cavium_id_base = atomic_add_return(smmu->num_context_banks,
+				&cavium_smmu_context_count);
+		smmu->cavium_id_base -= smmu->num_context_banks;
+	}

 	INIT_LIST_HEAD(&smmu->list);
 	spin_lock(&arm_smmu_devices_lock);
--
2.1.0

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Chalamarla, Tirumalesh]

Hi Will,

Do you want me to resend it with path version number change?

Thanks,
Tirumalesh.




On 3/4/16, 1:56 PM, "Chalamarla, Tirumalesh" <Tirumalesh.Chalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> wrote:

>Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
>namespaces; specifically within a given node SMMU0 and SMMU1 share,
>as does SMMU2 and SMMU3.
>
>This patch make sure ASID and VMID space is unique across cavium SMMUv2.
>
>changes from V3:
>	- Removed redundent variable.
>	- Used atomic_t for maintaining running total
>
>changes from V2:
>	- removed *_base from DT, and replaced with compatible string
>
>changes from V1:
>	- rebased on top of 16 bit VMID patch
>	- removed redundent options from DT
>	- insted of transform, DT now supplies starting ASID/VMID
>
>Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
>Signed-off-by: Akula Geethasowjanya <Geethasowjanya.Akula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
>---
> Documentation/arm64/silicon-errata.txt             |  1 +
> .../devicetree/bindings/iommu/arm,smmu.txt         |  1 +
> drivers/iommu/arm-smmu.c                           | 42 ++++++++++++++++------
> 3 files changed, 33 insertions(+), 11 deletions(-)
>
>diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
>index 58b71dd..3747a4b 100644
>--- a/Documentation/arm64/silicon-errata.txt
>+++ b/Documentation/arm64/silicon-errata.txt
>@@ -56,3 +56,4 @@ stable kernels.
> |                |                 |                 |                         |
> | Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
> | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
>+| Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
>diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
>index 7180745..19fe6f2 100644
>--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
>+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
>@@ -16,6 +16,7 @@ conditions.
>                         "arm,mmu-400"
>                         "arm,mmu-401"
>                         "arm,mmu-500"
>+                        "cavium,smmu-v2"
>
>                   depending on the particular implementation and/or the
>                   version of the architecture implemented.
>diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>index 247a469..e793b0a 100644
>--- a/drivers/iommu/arm-smmu.c
>+++ b/drivers/iommu/arm-smmu.c
>@@ -326,6 +326,11 @@ struct arm_smmu_device {
>
> 	struct list_head		list;
> 	struct rb_root			masters;
>+	/*
>+	 *The following fields are specific to Cavium, Thunder
>+	 */
>+	u32				cavium_id_base;
>+
> };
>
> struct arm_smmu_cfg {
>@@ -335,8 +340,8 @@ struct arm_smmu_cfg {
> };
> #define INVALID_IRPTNDX			0xff
>
>-#define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)
>-#define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)
>+#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
>+#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)
>
> enum arm_smmu_domain_stage {
> 	ARM_SMMU_DOMAIN_S1 = 0,
>@@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
> 	const char *prop;
> };
>
>+static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);
>+
> static struct arm_smmu_option_prop arm_smmu_options[] = {
> 	{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
> 	{ 0, NULL},
>@@ -575,11 +582,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)
>
> 	if (stage1) {
> 		base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
>-		writel_relaxed(ARM_SMMU_CB_ASID(cfg),
>+		writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg),
> 			       base + ARM_SMMU_CB_S1_TLBIASID);
> 	} else {
> 		base = ARM_SMMU_GR0(smmu);
>-		writel_relaxed(ARM_SMMU_CB_VMID(cfg),
>+		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg),
> 			       base + ARM_SMMU_GR0_TLBIVMID);
> 	}
>
>@@ -601,7 +608,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
>
> 		if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
> 			iova &= ~12UL;
>-			iova |= ARM_SMMU_CB_ASID(cfg);
>+			iova |= ARM_SMMU_CB_ASID(smmu, cfg);
> 			do {
> 				writel_relaxed(iova, reg);
> 				iova += granule;
>@@ -609,7 +616,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
> #ifdef CONFIG_64BIT
> 		} else {
> 			iova >>= 12;
>-			iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
>+			iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48;
> 			do {
> 				writeq_relaxed(iova, reg);
> 				iova += granule >> 12;
>@@ -629,7 +636,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
> #endif
> 	} else {
> 		reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
>-		writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
>+		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg);
> 	}
> }
>
>@@ -738,7 +745,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
> #endif
> 		/* 16-bit VMIDs live in CBA2R */
> 		if (smmu->features & ARM_SMMU_FEAT_VMID16)
>-			reg |= ARM_SMMU_CB_VMID(cfg) << CBA2R_VMID_SHIFT;
>+			reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT;
>
> 		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
> 	}
>@@ -757,7 +764,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
> 			(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
> 	} else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
> 		/* 8-bit VMIDs live in CBAR */
>-		reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
>+		reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT;
> 	}
> 	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
>
>@@ -765,11 +772,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
> 	if (stage1) {
> 		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
>
>-		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
>+		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
> 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);
>
> 		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
>-		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
>+		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
> 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1);
> 	} else {
> 		reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
>@@ -1717,6 +1724,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
> 	{ .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
> 	{ .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
> 	{ .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
>+	{ .compatible = "cavium,smmu-v2", .data = (void *)ARM_SMMU_V2 },
> 	{ },
> };
> MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
>@@ -1826,6 +1834,18 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
> 			goto out_free_irqs;
> 		}
> 	}
>+	/*
>+	 * Due to Errata#27704 CN88xx SMMUv2,supports  only shared ASID and VMID
>+	 * namespaces; specifically within a given node SMMU0 and SMMU1 share,
>+	 * as does SMMU2 and SMMU3. see if this is a Cavium SMMU, if so
>+	 * set asid and vmid base such that each SMMU gets unique
>+	 * asid/vmid space.
>+	 */
>+	if (of_device_is_compatible(dev->of_node, "cavium,smmu-v2")) {
>+		smmu->cavium_id_base = atomic_add_return(smmu->num_context_banks,
>+				&cavium_smmu_context_count);
>+		smmu->cavium_id_base -= smmu->num_context_banks;
>+	}
>
> 	INIT_LIST_HEAD(&smmu->list);
> 	spin_lock(&arm_smmu_devices_lock);
>--
>2.1.0
>

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Will Deacon]

On Thu, Mar 24, 2016 at 05:36:39PM +0000, Chalamarla, Tirumalesh wrote:
> Do you want me to resend it with path version number change?

Shouldn't be any need. I've queued this locally, and will push out when
I update my repo after the merge window.

Will

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Chalamarla, Tirumalesh]

Thanks. 




On 3/24/16, 10:51 AM, "Will Deacon" <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:

>On Thu, Mar 24, 2016 at 05:36:39PM +0000, Chalamarla, Tirumalesh wrote:
>> Do you want me to resend it with path version number change?
>
>Shouldn't be any need. I've queued this locally, and will push out when
>I update my repo after the merge window.
>
>Will

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Radha Mohan]

On Thu, Mar 24, 2016 at 11:29 AM, Chalamarla, Tirumalesh
<Tirumalesh.Chalamarla@caviumnetworks.com> wrote:
> Thanks.
>
>
>
>
> On 3/24/16, 10:51 AM, "Will Deacon" <will.deacon@arm.com> wrote:
>
>>On Thu, Mar 24, 2016 at 05:36:39PM +0000, Chalamarla, Tirumalesh wrote:
>>> Do you want me to resend it with path version number change?
>>
>>Shouldn't be any need. I've queued this locally, and will push out when
>>I update my repo after the merge window.
>>

Minor change that affects the kernel compilation.
I think it makes sense to resubmit the patch.

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 6ed7c3e..4aca5c1 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1834,8 +1834,8 @@ static int arm_smmu_device_dt_probe(struct
platform_device *pdev)
         * asid/vmid space.
         */
        if (of_device_is_compatible(dev->of_node, "cavium,smmu-v2")) {
-               smmu->cavium_id_base = atomic_read(cavium_smmu_context_count);
-               atomic_add(smmu->num_context_banks, cavium_smmu_context_count);
+               smmu->cavium_id_base = atomic_read(&cavium_smmu_context_count);
+               atomic_add(smmu->num_context_banks, &cavium_smmu_context_count);
        }

        list_add(&smmu->list, &arm_smmu_devices);

>>Will
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V4] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

[Radha Mohan]

On Mon, Mar 28, 2016 at 11:57 AM, Radha Mohan <mohun106@gmail.com> wrote:
> On Thu, Mar 24, 2016 at 11:29 AM, Chalamarla, Tirumalesh
> <Tirumalesh.Chalamarla@caviumnetworks.com> wrote:
>> Thanks.
>>
>>
>>
>>
>> On 3/24/16, 10:51 AM, "Will Deacon" <will.deacon@arm.com> wrote:
>>
>>>On Thu, Mar 24, 2016 at 05:36:39PM +0000, Chalamarla, Tirumalesh wrote:
>>>> Do you want me to resend it with path version number change?
>>>
>>>Shouldn't be any need. I've queued this locally, and will push out when
>>>I update my repo after the merge window.
>>>
>
> Minor change that affects the kernel compilation.
> I think it makes sense to resubmit the patch.
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index 6ed7c3e..4aca5c1 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -1834,8 +1834,8 @@ static int arm_smmu_device_dt_probe(struct
> platform_device *pdev)
>          * asid/vmid space.
>          */
>         if (of_device_is_compatible(dev->of_node, "cavium,smmu-v2")) {
> -               smmu->cavium_id_base = atomic_read(cavium_smmu_context_count);
> -               atomic_add(smmu->num_context_banks, cavium_smmu_context_count);
> +               smmu->cavium_id_base = atomic_read(&cavium_smmu_context_count);
> +               atomic_add(smmu->num_context_banks, &cavium_smmu_context_count);
>         }
>
>         list_add(&smmu->list, &arm_smmu_devices);
>

Ok, please ignore this, I missed the changes in between the thread :)

>>>Will
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel