From: Joerg Roedel <joro@8bytes.org>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org, Dmitry Osipenko <digetx@gmail.com>,
iommu@lists.linux-foundation.org,
Jon Hunter <jonathanh@nvidia.com>
Subject: Re: [PATCH 1/3] iommu/tegra-smmu: Use non-secure register for flushing
Date: Fri, 18 Oct 2019 11:46:31 +0200 [thread overview]
Message-ID: <20191018094630.GA4670@8bytes.org> (raw)
In-Reply-To: <20191016115026.1768745-1-thierry.reding@gmail.com>
On Wed, Oct 16, 2019 at 01:50:24PM +0200, Thierry Reding wrote:
> From: Navneet Kumar <navneetk@nvidia.com>
>
> Use PTB_ASID instead of SMMU_CONFIG to flush smmu.
> PTB_ASID can be accessed from non-secure mode, SMMU_CONFIG cannot be.
> Using SMMU_CONFIG could pose a problem when kernel doesn't have secure
> mode access enabled from boot.
>
> Signed-off-by: Navneet Kumar <navneetk@nvidia.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
> Tested-by: Dmitry Osipenko <digetx@gmail.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/iommu/tegra-smmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied all, thanks.
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prev parent reply other threads:[~2019-10-18 9:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-16 11:50 [PATCH 1/3] iommu/tegra-smmu: Use non-secure register for flushing Thierry Reding
2019-10-16 11:50 ` [PATCH 2/3] iommu/tegra-smmu: Fix client enablement order Thierry Reding
2019-10-16 11:50 ` [PATCH 3/3] iommu/tegra-smmu: Fix page tables in > 4 GiB memory Thierry Reding
2019-10-18 9:46 ` Joerg Roedel [this message]
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