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From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux-foundation.org
Subject: [PATCH 15/22] iommu/vt-d: Add PASID_FLAG_FL5LP for first-level pasid setup
Date: Thu,  2 Jan 2020 08:18:16 +0800	[thread overview]
Message-ID: <20200102001823.21976-16-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20200102001823.21976-1-baolu.lu@linux.intel.com>

Current intel_pasid_setup_first_level() use 5-level paging for
first level translation if CPUs use 5-level paging mode too.
This makes sense for SVA usages since the page table is shared
between CPUs and IOMMUs. But it makes no sense if we only want
to use first level for IOVA translation. Add PASID_FLAG_FL5LP
bit in the flags which indicates whether the 5-level paging
mode should be used.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel-pasid.c | 7 ++-----
 drivers/iommu/intel-pasid.h | 6 ++++++
 drivers/iommu/intel-svm.c   | 8 ++++++--
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
index 3cb569e76642..22b30f10b396 100644
--- a/drivers/iommu/intel-pasid.c
+++ b/drivers/iommu/intel-pasid.c
@@ -477,18 +477,15 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
 		pasid_set_sre(pte);
 	}
 
-#ifdef CONFIG_X86
-	/* Both CPU and IOMMU paging mode need to match */
-	if (cpu_feature_enabled(X86_FEATURE_LA57)) {
+	if (flags & PASID_FLAG_FL5LP) {
 		if (cap_5lp_support(iommu->cap)) {
 			pasid_set_flpm(pte, 1);
 		} else {
-			pr_err("VT-d has no 5-level paging support for CPU\n");
+			pr_err("No 5-level paging support for first-level\n");
 			pasid_clear_entry(pte);
 			return -EINVAL;
 		}
 	}
-#endif /* CONFIG_X86 */
 
 	pasid_set_domain_id(pte, did);
 	pasid_set_address_width(pte, iommu->agaw);
diff --git a/drivers/iommu/intel-pasid.h b/drivers/iommu/intel-pasid.h
index fc8cd8f17de1..92de6df24ccb 100644
--- a/drivers/iommu/intel-pasid.h
+++ b/drivers/iommu/intel-pasid.h
@@ -37,6 +37,12 @@
  */
 #define PASID_FLAG_SUPERVISOR_MODE	BIT(0)
 
+/*
+ * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
+ * level translation, otherwise, 4-level paging will be used.
+ */
+#define PASID_FLAG_FL5LP		BIT(1)
+
 struct pasid_dir_entry {
 	u64 val;
 };
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index 04023033b79f..d7f2a5358900 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -364,7 +364,9 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
 		ret = intel_pasid_setup_first_level(iommu, dev,
 				mm ? mm->pgd : init_mm.pgd,
 				svm->pasid, FLPT_DEFAULT_DID,
-				mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
+				(mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
+				(cpu_feature_enabled(X86_FEATURE_LA57) ?
+				 PASID_FLAG_FL5LP : 0));
 		spin_unlock(&iommu->lock);
 		if (ret) {
 			if (mm)
@@ -385,7 +387,9 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
 		ret = intel_pasid_setup_first_level(iommu, dev,
 						mm ? mm->pgd : init_mm.pgd,
 						svm->pasid, FLPT_DEFAULT_DID,
-						mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
+						(mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
+						(cpu_feature_enabled(X86_FEATURE_LA57) ?
+						PASID_FLAG_FL5LP : 0));
 		spin_unlock(&iommu->lock);
 		if (ret) {
 			kfree(sdev);
-- 
2.17.1

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  parent reply	other threads:[~2020-01-02  0:19 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-02  0:18 [PULL REQUEST] iommu/vt-d: patches for v5.6 Lu Baolu
2020-01-02  0:18 ` [PATCH 01/22] iommu/vt-d: Add Kconfig option to enable/disable scalable mode Lu Baolu
2020-01-02  0:18 ` [PATCH 02/22] iommu/vt-d: Fix CPU and IOMMU SVM feature matching checks Lu Baolu
2020-01-02  0:18 ` [PATCH 03/22] iommu/vt-d: Match CPU and IOMMU paging mode Lu Baolu
2020-01-02  0:18 ` [PATCH 04/22] iommu/vt-d: Reject SVM bind for failed capability check Lu Baolu
2020-01-02  0:18 ` [PATCH 05/22] iommu/vt-d: Avoid duplicated code for PASID setup Lu Baolu
2020-01-02  0:18 ` [PATCH 06/22] iommu/vt-d: Fix off-by-one in PASID allocation Lu Baolu
2020-01-02  0:18 ` [PATCH 07/22] iommu/vt-d: Replace Intel specific PASID allocator with IOASID Lu Baolu
2020-01-02  0:18 ` [PATCH 08/22] iommu/vt-d: Avoid sending invalid page response Lu Baolu
2020-01-02  0:18 ` [PATCH 09/22] iommu/vt-d: Misc macro clean up for SVM Lu Baolu
2020-01-02  0:18 ` [PATCH 10/22] iommu/vt-d: trace: Extend map_sg trace event Lu Baolu
2020-01-02  0:18 ` [PATCH 11/22] iommu/vt-d: Avoid iova flush queue in strict mode Lu Baolu
2020-01-02  0:18 ` [PATCH 12/22] iommu/vt-d: Loose requirement for flush queue initializaton Lu Baolu
2020-01-02  0:18 ` [PATCH 13/22] iommu/vt-d: Identify domains using first level page table Lu Baolu
2020-01-02  0:18 ` [PATCH 14/22] iommu/vt-d: Add set domain DOMAIN_ATTR_NESTING attr Lu Baolu
2020-01-02  0:18 ` Lu Baolu [this message]
2020-01-02  0:18 ` [PATCH 16/22] iommu/vt-d: Setup pasid entries for iova over first level Lu Baolu
2020-01-02  0:18 ` [PATCH 17/22] iommu/vt-d: Flush PASID-based iotlb " Lu Baolu
2020-01-02  0:18 ` [PATCH 18/22] iommu/vt-d: Make first level IOVA canonical Lu Baolu
2020-01-02  0:18 ` [PATCH 19/22] iommu/vt-d: Update first level super page capability Lu Baolu
2020-01-02  0:18 ` [PATCH 20/22] iommu/vt-d: Use iova over first level Lu Baolu
2020-01-02  0:18 ` [PATCH 21/22] iommu/vt-d: debugfs: Add support to show page table internals Lu Baolu
2020-01-02  0:18 ` [PATCH 22/22] iommu/vt-d: Add a quirk flag for scope mismatched devices Lu Baolu
2020-01-02  2:11   ` Roland Dreier via iommu
2020-01-02  2:14     ` Lu Baolu
2020-01-02  2:25       ` Roland Dreier via iommu
2020-01-02  2:34         ` Lu Baolu
2020-01-03  0:32         ` Lu Baolu
2020-01-04 16:52           ` Roland Dreier via iommu
2020-01-05  3:43             ` Lu Baolu
2020-01-06 17:05         ` Jerry Snitselaar
2020-01-07  0:35           ` Lu Baolu
2020-01-07  1:30             ` Jerry Snitselaar
2020-01-07  1:47               ` Lu Baolu
2020-01-09  0:12                 ` Roland Dreier via iommu
2020-01-08 14:16   ` Christoph Hellwig
2020-01-08 23:28     ` Lu Baolu
2020-01-09  7:06       ` Christoph Hellwig
2020-01-09  8:53         ` Lu Baolu
2020-01-09  8:56           ` 答复: " Jim,Yan
2020-01-07 13:06 ` [PULL REQUEST] iommu/vt-d: patches for v5.6 Joerg Roedel

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