From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux-foundation.org
Subject: [PATCH 02/22] iommu/vt-d: Fix CPU and IOMMU SVM feature matching checks
Date: Thu, 2 Jan 2020 08:18:03 +0800 [thread overview]
Message-ID: <20200102001823.21976-3-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20200102001823.21976-1-baolu.lu@linux.intel.com>
From: Jacob Pan <jacob.jun.pan@linux.intel.com>
Shared Virtual Memory(SVM) is based on a collective set of hardware
features detected at runtime. There are requirements for matching CPU
and IOMMU capabilities.
The current code checks CPU and IOMMU feature set for SVM support but
the result is never stored nor used. Therefore, SVM can still be used
even when these checks failed. The consequences can be:
1. CPU uses 5-level paging mode for virtual address of 57 bits, but
IOMMU can only support 4-level paging mode with 48 bits address for DMA.
2. 1GB page size is used by CPU but IOMMU does not support it. VT-d
unrecoverable faults may be generated.
The best solution to fix these problems is to prevent them in the first
place.
This patch consolidates code for checking PASID, CPU vs. IOMMU paging
mode compatibility, as well as provides specific error messages for
each failed checks. On sane hardware configurations, these error message
shall never appear in kernel log.
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel-iommu.c | 10 ++--------
drivers/iommu/intel-svm.c | 40 +++++++++++++++++++++++++------------
include/linux/intel-iommu.h | 5 ++++-
3 files changed, 33 insertions(+), 22 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 26c40134817e..5328e2ed2dd3 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -3299,10 +3299,7 @@ static int __init init_dmars(void)
if (!ecap_pass_through(iommu->ecap))
hw_pass_through = 0;
-#ifdef CONFIG_INTEL_IOMMU_SVM
- if (pasid_supported(iommu))
- intel_svm_init(iommu);
-#endif
+ intel_svm_check(iommu);
}
/*
@@ -4495,10 +4492,7 @@ static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
if (ret)
goto out;
-#ifdef CONFIG_INTEL_IOMMU_SVM
- if (pasid_supported(iommu))
- intel_svm_init(iommu);
-#endif
+ intel_svm_check(iommu);
if (dmaru->ignored) {
/*
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index dca88f9fdf29..e4a5d542b84f 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -23,19 +23,6 @@
static irqreturn_t prq_event_thread(int irq, void *d);
-int intel_svm_init(struct intel_iommu *iommu)
-{
- if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
- !cap_fl1gp_support(iommu->cap))
- return -EINVAL;
-
- if (cpu_feature_enabled(X86_FEATURE_LA57) &&
- !cap_5lp_support(iommu->cap))
- return -EINVAL;
-
- return 0;
-}
-
#define PRQ_ORDER 0
int intel_svm_enable_prq(struct intel_iommu *iommu)
@@ -99,6 +86,33 @@ int intel_svm_finish_prq(struct intel_iommu *iommu)
return 0;
}
+static inline bool intel_svm_capable(struct intel_iommu *iommu)
+{
+ return iommu->flags & VTD_FLAG_SVM_CAPABLE;
+}
+
+void intel_svm_check(struct intel_iommu *iommu)
+{
+ if (!pasid_supported(iommu))
+ return;
+
+ if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
+ !cap_fl1gp_support(iommu->cap)) {
+ pr_err("%s SVM disabled, incompatible 1GB page capability\n",
+ iommu->name);
+ return;
+ }
+
+ if (cpu_feature_enabled(X86_FEATURE_LA57) &&
+ !cap_5lp_support(iommu->cap)) {
+ pr_err("%s SVM disabled, incompatible paging mode\n",
+ iommu->name);
+ return;
+ }
+
+ iommu->flags |= VTD_FLAG_SVM_CAPABLE;
+}
+
static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
unsigned long address, unsigned long pages, int ih)
{
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 6d8bf4bdf240..aaece25c055f 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -435,6 +435,7 @@ enum {
#define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
+#define VTD_FLAG_SVM_CAPABLE (1 << 2)
extern int intel_iommu_sm;
@@ -658,7 +659,7 @@ void iommu_flush_write_buffer(struct intel_iommu *iommu);
int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);
#ifdef CONFIG_INTEL_IOMMU_SVM
-int intel_svm_init(struct intel_iommu *iommu);
+extern void intel_svm_check(struct intel_iommu *iommu);
extern int intel_svm_enable_prq(struct intel_iommu *iommu);
extern int intel_svm_finish_prq(struct intel_iommu *iommu);
@@ -686,6 +687,8 @@ struct intel_svm {
};
extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
+#else
+static inline void intel_svm_check(struct intel_iommu *iommu) {}
#endif
#ifdef CONFIG_INTEL_IOMMU_DEBUGFS
--
2.17.1
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next prev parent reply other threads:[~2020-01-02 0:19 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-02 0:18 [PULL REQUEST] iommu/vt-d: patches for v5.6 Lu Baolu
2020-01-02 0:18 ` [PATCH 01/22] iommu/vt-d: Add Kconfig option to enable/disable scalable mode Lu Baolu
2020-01-02 0:18 ` Lu Baolu [this message]
2020-01-02 0:18 ` [PATCH 03/22] iommu/vt-d: Match CPU and IOMMU paging mode Lu Baolu
2020-01-02 0:18 ` [PATCH 04/22] iommu/vt-d: Reject SVM bind for failed capability check Lu Baolu
2020-01-02 0:18 ` [PATCH 05/22] iommu/vt-d: Avoid duplicated code for PASID setup Lu Baolu
2020-01-02 0:18 ` [PATCH 06/22] iommu/vt-d: Fix off-by-one in PASID allocation Lu Baolu
2020-01-02 0:18 ` [PATCH 07/22] iommu/vt-d: Replace Intel specific PASID allocator with IOASID Lu Baolu
2020-01-02 0:18 ` [PATCH 08/22] iommu/vt-d: Avoid sending invalid page response Lu Baolu
2020-01-02 0:18 ` [PATCH 09/22] iommu/vt-d: Misc macro clean up for SVM Lu Baolu
2020-01-02 0:18 ` [PATCH 10/22] iommu/vt-d: trace: Extend map_sg trace event Lu Baolu
2020-01-02 0:18 ` [PATCH 11/22] iommu/vt-d: Avoid iova flush queue in strict mode Lu Baolu
2020-01-02 0:18 ` [PATCH 12/22] iommu/vt-d: Loose requirement for flush queue initializaton Lu Baolu
2020-01-02 0:18 ` [PATCH 13/22] iommu/vt-d: Identify domains using first level page table Lu Baolu
2020-01-02 0:18 ` [PATCH 14/22] iommu/vt-d: Add set domain DOMAIN_ATTR_NESTING attr Lu Baolu
2020-01-02 0:18 ` [PATCH 15/22] iommu/vt-d: Add PASID_FLAG_FL5LP for first-level pasid setup Lu Baolu
2020-01-02 0:18 ` [PATCH 16/22] iommu/vt-d: Setup pasid entries for iova over first level Lu Baolu
2020-01-02 0:18 ` [PATCH 17/22] iommu/vt-d: Flush PASID-based iotlb " Lu Baolu
2020-01-02 0:18 ` [PATCH 18/22] iommu/vt-d: Make first level IOVA canonical Lu Baolu
2020-01-02 0:18 ` [PATCH 19/22] iommu/vt-d: Update first level super page capability Lu Baolu
2020-01-02 0:18 ` [PATCH 20/22] iommu/vt-d: Use iova over first level Lu Baolu
2020-01-02 0:18 ` [PATCH 21/22] iommu/vt-d: debugfs: Add support to show page table internals Lu Baolu
2020-01-02 0:18 ` [PATCH 22/22] iommu/vt-d: Add a quirk flag for scope mismatched devices Lu Baolu
2020-01-02 2:11 ` Roland Dreier via iommu
2020-01-02 2:14 ` Lu Baolu
2020-01-02 2:25 ` Roland Dreier via iommu
2020-01-02 2:34 ` Lu Baolu
2020-01-03 0:32 ` Lu Baolu
2020-01-04 16:52 ` Roland Dreier via iommu
2020-01-05 3:43 ` Lu Baolu
2020-01-06 17:05 ` Jerry Snitselaar
2020-01-07 0:35 ` Lu Baolu
2020-01-07 1:30 ` Jerry Snitselaar
2020-01-07 1:47 ` Lu Baolu
2020-01-09 0:12 ` Roland Dreier via iommu
2020-01-08 14:16 ` Christoph Hellwig
2020-01-08 23:28 ` Lu Baolu
2020-01-09 7:06 ` Christoph Hellwig
2020-01-09 8:53 ` Lu Baolu
2020-01-09 8:56 ` 答复: " Jim,Yan
2020-01-07 13:06 ` [PULL REQUEST] iommu/vt-d: patches for v5.6 Joerg Roedel
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