From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux-foundation.org
Subject: [PATCH 02/12] iommu/vt-d: Remove global page support in devTLB flush
Date: Fri, 24 Jul 2020 09:49:15 +0800 [thread overview]
Message-ID: <20200724014925.15523-3-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20200724014925.15523-1-baolu.lu@linux.intel.com>
From: Jacob Pan <jacob.jun.pan@linux.intel.com>
Global pages support is removed from VT-d spec 3.0 for dev TLB
invalidation. This patch is to remove the bits for vSVA. Similar change
already made for the native SVA. See the link below.
Link: https://lore.kernel.org/linux-iommu/20190830142919.GE11578@8bytes.org/T/
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel/dmar.c | 4 +---
drivers/iommu/intel/iommu.c | 4 ++--
include/linux/intel-iommu.h | 3 +--
3 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index 16f47041f1bf..a46d8d4abdb8 100644
--- a/drivers/iommu/intel/dmar.c
+++ b/drivers/iommu/intel/dmar.c
@@ -1439,8 +1439,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
/* PASID-based device IOTLB Invalidate */
void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
- u32 pasid, u16 qdep, u64 addr,
- unsigned int size_order, u64 granu)
+ u32 pasid, u16 qdep, u64 addr, unsigned int size_order)
{
unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
@@ -1448,7 +1447,6 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
QI_DEV_IOTLB_PFSID(pfsid);
- desc.qw1 = QI_DEV_EIOTLB_GLOB(granu);
/*
* If S bit is 0, we only flush a single page. If S bit is set,
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index cc158250f45e..888697dd240a 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -5480,7 +5480,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev,
info->pfsid, pasid,
info->ats_qdep,
inv_info->addr_info.addr,
- size, granu);
+ size);
break;
case IOMMU_CACHE_INV_TYPE_DEV_IOTLB:
if (info->ats_enabled)
@@ -5488,7 +5488,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev,
info->pfsid, pasid,
info->ats_qdep,
inv_info->addr_info.addr,
- size, granu);
+ size);
else
pr_warn_ratelimited("Passdown device IOTLB flush w/o ATS!\n");
break;
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 711bdca975be..383847b859a1 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -381,7 +381,6 @@ enum {
#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
-#define QI_DEV_EIOTLB_GLOB(g) ((u64)(g) & 0x1)
#define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32)
#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
@@ -707,7 +706,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
u32 pasid, u16 qdep, u64 addr,
- unsigned int size_order, u64 granu);
+ unsigned int size_order);
void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,
int pasid);
--
2.17.1
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next prev parent reply other threads:[~2020-07-24 1:54 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-24 1:49 [PATCH 00/12] [PULL REQUEST] iommu/vt-d: patches for v5.9 Lu Baolu
2020-07-24 1:49 ` [PATCH 01/12] iommu/vt-d: Enforce PASID devTLB field mask Lu Baolu
2020-07-24 1:49 ` Lu Baolu [this message]
2020-07-24 1:49 ` [PATCH 03/12] iommu/vt-d: Fix PASID devTLB invalidation Lu Baolu
2020-07-24 1:49 ` [PATCH 04/12] iommu/vt-d: Handle non-page aligned address Lu Baolu
2020-07-24 1:49 ` [PATCH 05/12] iommu/vt-d: Fix devTLB flush for vSVA Lu Baolu
2020-07-24 1:49 ` [PATCH 06/12] iommu/vt-d: Warn on out-of-range invalidation address Lu Baolu
2020-07-24 1:49 ` [PATCH 07/12] iommu/vt-d: Disable multiple GPASID-dev bind Lu Baolu
2020-07-24 1:49 ` [PATCH 08/12] iommu/vt-d: Refactor device_to_iommu() helper Lu Baolu
2020-07-24 1:49 ` [PATCH 09/12] iommu/vt-d: Add a helper to get svm and sdev for pasid Lu Baolu
2020-07-24 1:49 ` [PATCH 10/12] iommu/vt-d: Report page request faults for guest SVA Lu Baolu
2020-07-24 1:49 ` [PATCH 11/12] iommu/vt-d: Add page response ops support Lu Baolu
2020-07-24 1:49 ` [PATCH 12/12] iommu/vt-d: Rename intel-pasid.h to pasid.h Lu Baolu
2020-07-24 8:55 ` [PATCH 00/12] [PULL REQUEST] iommu/vt-d: patches for v5.9 Joerg Roedel
2020-07-24 9:08 ` Lu Baolu
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