From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>
Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 4/5] iommu/vt-d: Use user privilege for RID2PASID translation
Date: Sat, 20 Mar 2021 10:54:14 +0800 [thread overview]
Message-ID: <20210320025415.641201-5-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20210320025415.641201-1-baolu.lu@linux.intel.com>
When first-level page tables are used for IOVA translation, we use user
privilege by setting U/S bit in the page table entry. This is to make it
consistent with the second level translation, where the U/S enforcement
is not available. Clear the SRE (Supervisor Request Enable) field in the
pasid table entry of RID2PASID so that requests requesting the supervisor
privilege are blocked and treated as DMA remapping faults.
Suggested-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel/iommu.c | 7 +++++--
drivers/iommu/intel/pasid.c | 3 ++-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 868f195f55ff..7354f9ce47d8 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -2494,9 +2494,9 @@ static int domain_setup_first_level(struct intel_iommu *iommu,
struct device *dev,
u32 pasid)
{
- int flags = PASID_FLAG_SUPERVISOR_MODE;
struct dma_pte *pgd = domain->pgd;
int agaw, level;
+ int flags = 0;
/*
* Skip top levels of page tables for iommu which has
@@ -2512,7 +2512,10 @@ static int domain_setup_first_level(struct intel_iommu *iommu,
if (level != 4 && level != 5)
return -EINVAL;
- flags |= (level == 5) ? PASID_FLAG_FL5LP : 0;
+ if (pasid != PASID_RID2PASID)
+ flags |= PASID_FLAG_SUPERVISOR_MODE;
+ if (level == 5)
+ flags |= PASID_FLAG_FL5LP;
return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid,
domain->iommu_did[iommu->seq_id],
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 0bf7e0a76890..dd69df5a188a 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -673,7 +673,8 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu,
* Since it is a second level only translation setup, we should
* set SRE bit as well (addresses are expected to be GPAs).
*/
- pasid_set_sre(pte);
+ if (pasid != PASID_RID2PASID)
+ pasid_set_sre(pte);
pasid_set_present(pte);
pasid_flush_caches(iommu, pte, pasid, did);
--
2.25.1
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next prev parent reply other threads:[~2021-03-20 3:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-20 2:54 [PATCH v2 0/5] iommu/vt-d: Several misc fixes Lu Baolu
2021-03-20 2:54 ` [PATCH v2 1/5] iommu/vt-d: Report the right page fault address Lu Baolu
2021-03-20 2:54 ` [PATCH v2 2/5] iommu/vt-d: Remove WO permissions on second-level paging entries Lu Baolu
2021-03-20 2:54 ` [PATCH v2 3/5] iommu/vt-d: Invalidate PASID cache when root/context entry changed Lu Baolu
2021-03-20 2:54 ` Lu Baolu [this message]
2021-04-06 0:58 ` [PATCH v2 4/5] iommu/vt-d: Use user privilege for RID2PASID translation Lu Baolu
2021-03-20 2:54 ` [PATCH v2 5/5] iommu/vt-d: Avoid unnecessary cache flush in pasid entry teardown Lu Baolu
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