From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>
Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 5/5] iommu/vt-d: Avoid unnecessary cache flush in pasid entry teardown
Date: Sat, 20 Mar 2021 10:54:15 +0800 [thread overview]
Message-ID: <20210320025415.641201-6-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20210320025415.641201-1-baolu.lu@linux.intel.com>
When a present pasid entry is disassembled, all kinds of pasid related
caches need to be flushed. But when a pasid entry is not being used
(PRESENT bit not set), we don't need to do this. Check the PRESENT bit
in intel_pasid_tear_down_entry() and avoid flushing caches if it's not
set.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel/pasid.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index dd69df5a188a..7a73385edcc0 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -502,6 +502,9 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev,
if (WARN_ON(!pte))
return;
+ if (!(pte->val[0] & PASID_PTE_PRESENT))
+ return;
+
did = pasid_get_domain_id(pte);
intel_pasid_clear_entry(dev, pasid, fault_ignore);
--
2.25.1
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prev parent reply other threads:[~2021-03-20 3:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-20 2:54 [PATCH v2 0/5] iommu/vt-d: Several misc fixes Lu Baolu
2021-03-20 2:54 ` [PATCH v2 1/5] iommu/vt-d: Report the right page fault address Lu Baolu
2021-03-20 2:54 ` [PATCH v2 2/5] iommu/vt-d: Remove WO permissions on second-level paging entries Lu Baolu
2021-03-20 2:54 ` [PATCH v2 3/5] iommu/vt-d: Invalidate PASID cache when root/context entry changed Lu Baolu
2021-03-20 2:54 ` [PATCH v2 4/5] iommu/vt-d: Use user privilege for RID2PASID translation Lu Baolu
2021-04-06 0:58 ` Lu Baolu
2021-03-20 2:54 ` Lu Baolu [this message]
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