* [PATCH trivial] iommu/amd: Rearrange DTE bit definations
@ 2023-06-19 13:19 Vasant Hegde
2023-06-20 18:21 ` Jerry Snitselaar
2023-08-07 14:08 ` Vasant Hegde
0 siblings, 2 replies; 3+ messages in thread
From: Vasant Hegde @ 2023-06-19 13:19 UTC (permalink / raw)
To: iommu, joro; +Cc: suravee.suthikulpanit, Vasant Hegde, Jerry Snitselaar
Rearrage according to 64bit word they are in.
Note that I have not rearranged gcr3 related macros even though
they belong to different 64bit word as its easy to read it in
current format.
No functional changes intended.
Suggested-by: Jerry Snitselaar <jsnitsel@redhat.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
---
drivers/iommu/amd/amd_iommu_types.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 53443d6f7b13..082c57b8c2d6 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -381,15 +381,15 @@
*/
#define DTE_FLAG_V BIT_ULL(0)
#define DTE_FLAG_TV BIT_ULL(1)
+#define DTE_FLAG_GIOV BIT_ULL(54)
+#define DTE_FLAG_GV BIT_ULL(55)
+#define DTE_GLX_SHIFT (56)
+#define DTE_GLX_MASK (3)
#define DTE_FLAG_IR BIT_ULL(61)
#define DTE_FLAG_IW BIT_ULL(62)
#define DTE_FLAG_IOTLB BIT_ULL(32)
-#define DTE_FLAG_GIOV BIT_ULL(54)
-#define DTE_FLAG_GV BIT_ULL(55)
#define DTE_FLAG_MASK (0x3ffULL << 32)
-#define DTE_GLX_SHIFT (56)
-#define DTE_GLX_MASK (3)
#define DEV_DOMID_MASK 0xffffULL
#define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH trivial] iommu/amd: Rearrange DTE bit definations
2023-06-19 13:19 [PATCH trivial] iommu/amd: Rearrange DTE bit definations Vasant Hegde
@ 2023-06-20 18:21 ` Jerry Snitselaar
2023-08-07 14:08 ` Vasant Hegde
1 sibling, 0 replies; 3+ messages in thread
From: Jerry Snitselaar @ 2023-06-20 18:21 UTC (permalink / raw)
To: Vasant Hegde; +Cc: iommu, joro, suravee.suthikulpanit
On Mon, Jun 19, 2023 at 01:19:08PM +0000, Vasant Hegde wrote:
> Rearrage according to 64bit word they are in.
>
> Note that I have not rearranged gcr3 related macros even though
> they belong to different 64bit word as its easy to read it in
> current format.
>
> No functional changes intended.
>
> Suggested-by: Jerry Snitselaar <jsnitsel@redhat.com>
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
> ---
> drivers/iommu/amd/amd_iommu_types.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index 53443d6f7b13..082c57b8c2d6 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -381,15 +381,15 @@
> */
> #define DTE_FLAG_V BIT_ULL(0)
> #define DTE_FLAG_TV BIT_ULL(1)
> +#define DTE_FLAG_GIOV BIT_ULL(54)
> +#define DTE_FLAG_GV BIT_ULL(55)
> +#define DTE_GLX_SHIFT (56)
> +#define DTE_GLX_MASK (3)
> #define DTE_FLAG_IR BIT_ULL(61)
> #define DTE_FLAG_IW BIT_ULL(62)
>
> #define DTE_FLAG_IOTLB BIT_ULL(32)
> -#define DTE_FLAG_GIOV BIT_ULL(54)
> -#define DTE_FLAG_GV BIT_ULL(55)
> #define DTE_FLAG_MASK (0x3ffULL << 32)
> -#define DTE_GLX_SHIFT (56)
> -#define DTE_GLX_MASK (3)
> #define DEV_DOMID_MASK 0xffffULL
>
> #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
> --
> 2.31.1
>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH trivial] iommu/amd: Rearrange DTE bit definations
2023-06-19 13:19 [PATCH trivial] iommu/amd: Rearrange DTE bit definations Vasant Hegde
2023-06-20 18:21 ` Jerry Snitselaar
@ 2023-08-07 14:08 ` Vasant Hegde
1 sibling, 0 replies; 3+ messages in thread
From: Vasant Hegde @ 2023-08-07 14:08 UTC (permalink / raw)
To: iommu, joro; +Cc: suravee.suthikulpanit, Jerry Snitselaar
Hi Joerg,
On 6/19/2023 6:49 PM, Vasant Hegde wrote:
> Rearrage according to 64bit word they are in.
>
> Note that I have not rearranged gcr3 related macros even though
> they belong to different 64bit word as its easy to read it in
> current format.
Ping. Did you get a chance a look into this one?
-Vasant
>
> No functional changes intended.
>
> Suggested-by: Jerry Snitselaar <jsnitsel@redhat.com>
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
> ---
> drivers/iommu/amd/amd_iommu_types.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index 53443d6f7b13..082c57b8c2d6 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -381,15 +381,15 @@
> */
> #define DTE_FLAG_V BIT_ULL(0)
> #define DTE_FLAG_TV BIT_ULL(1)
> +#define DTE_FLAG_GIOV BIT_ULL(54)
> +#define DTE_FLAG_GV BIT_ULL(55)
> +#define DTE_GLX_SHIFT (56)
> +#define DTE_GLX_MASK (3)
> #define DTE_FLAG_IR BIT_ULL(61)
> #define DTE_FLAG_IW BIT_ULL(62)
>
> #define DTE_FLAG_IOTLB BIT_ULL(32)
> -#define DTE_FLAG_GIOV BIT_ULL(54)
> -#define DTE_FLAG_GV BIT_ULL(55)
> #define DTE_FLAG_MASK (0x3ffULL << 32)
> -#define DTE_GLX_SHIFT (56)
> -#define DTE_GLX_MASK (3)
> #define DEV_DOMID_MASK 0xffffULL
>
> #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-06-19 13:19 [PATCH trivial] iommu/amd: Rearrange DTE bit definations Vasant Hegde
2023-06-20 18:21 ` Jerry Snitselaar
2023-08-07 14:08 ` Vasant Hegde
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