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From: Jason Gunthorpe <jgg@nvidia.com>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org, suravee.suthikulpanit@amd.com
Subject: Re: [PATCH v1 10/13] iommu/amd: Consolidate domain flush logic
Date: Mon, 6 Nov 2023 09:13:03 -0400	[thread overview]
Message-ID: <20231106131303.GG4488@nvidia.com> (raw)
In-Reply-To: <5e95d78b-4c42-6596-c1b0-057e044197fc@amd.com>

On Mon, Nov 06, 2023 at 04:42:17PM +0530, Vasant Hegde wrote:
> 
> 
> On 11/5/2023 11:25 PM, Jason Gunthorpe wrote:
> > On Fri, Oct 06, 2023 at 10:16:21AM +0000, Vasant Hegde wrote:
> > 
> >> @@ -1557,7 +1583,9 @@ static void domain_flush_pages(struct protection_domain *domain,
> >>  void amd_iommu_domain_flush_pages(struct protection_domain *pdom,
> >>  				  u64 address, size_t size)
> >>  {
> >> -	return domain_flush_pages(pdom, address, size);
> >> +	ioasid_t pasid = pdom_get_default_pasid(pdom);
> >> +
> >> +	return domain_flush_pages(pdom, pasid, address, size);
> >>  }
> > 
> > There should be no such thing as a pasid for a domain. There should
> 
> We do have default PASID (zero) when we boot in v2 page table mode.

That is the PASID for a RID, not the PASID or a domain.

> > not be an api called pdom_get_default_pasid(), it is nonsensical.
> 
> But we have single command to deal with all IOMMU TLB flush.

This is probably a mistake..

> I have a choice of doing all checks in low level function (what this patch does)
>  -OR- add checks in all API path (like flush_iotlb_all, iotlb_sync, etc). If
> that's what preferred I can do that.

Well, you should not have concepts like the 'pasid of a domain' and
you should not encode the v1/v2 type into the pasid. I didn't look
closely how to sort that out to say exactly.

I can say that in SMMUv3 structuring it so that the attach op at the
top of the call chain knows what to do, and called a bunch of specific
helpers was reasonable. We know at the op level if we are going to do
a V1 or V2 invalidation because the OP itself already knows if it is
working on a V1/V2 iommu domain due to how it has to load the domain
into the DTE/GCR3.

So if you have:

   invalidate_iotlb_range/all_v1(domain)
   invalidate_iotlb_range/all_v2(device, pasid)
   invalidate_iotlb_full_v2(device)  // Clean every pasid
   invalidate_atc_range/all(domain)
     invalidate_atc_device_range_all(device, pasid)
   invalidate_atc_full(device) // Clean every pasid

As working functions then the ops should be writable to know exactly
which of those call based on the op.

For instance, if you have a v1 page table then you should have a v1
specific flush op that does:

   invalidate_iotlb_range/all_v1(domain)
   if (domain->ats in use)
     invalidate_atc_range/all(domain)

No maze.

Jason

  reply	other threads:[~2023-11-06 13:13 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-06 10:16 [PATCH v1 00/13] Improve TLB invalidation logic Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 01/13] iommu/amd: Rename iommu_flush_all_caches() -> amd_iommu_flush_all_caches() Vasant Hegde
2023-11-03 18:08   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 02/13] iommu/amd: Remove redundant domain flush from attach_device() Vasant Hegde
2023-11-03 18:09   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 03/13] iommu/amd: Remove redundant passing of PDE bit Vasant Hegde
2023-11-03 18:11   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 04/13] iommu/amd: Add support to invalidate multiple guest pages Vasant Hegde
2023-11-03 18:23   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 05/13] iommu/amd: Refactor IOMMU tlb invalidation code Vasant Hegde
2023-11-03 18:25   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 06/13] iommu/amd: Refactor device iotlb " Vasant Hegde
2023-11-03 18:25   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 07/13] iommu/amd: Consolidate device IOTLB flush code Vasant Hegde
2023-11-03 18:44   ` Jason Gunthorpe
2023-11-06 11:39     ` Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 08/13] iommu/amd: Consolidate amd_iommu_domain_flush_complete() call Vasant Hegde
2023-11-03 18:45   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 09/13] iommu/amd: Refactor domain flush global function Vasant Hegde
2023-11-05 17:52   ` Jason Gunthorpe
2023-11-06 10:53     ` Vasant Hegde
2023-11-06 13:01       ` Jason Gunthorpe
2023-11-07  4:53         ` Vasant Hegde
2023-11-07 13:11           ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 10/13] iommu/amd: Consolidate domain flush logic Vasant Hegde
2023-11-05 17:55   ` Jason Gunthorpe
2023-11-06 11:12     ` Vasant Hegde
2023-11-06 13:13       ` Jason Gunthorpe [this message]
2023-11-07  4:44         ` Vasant Hegde
2023-11-07 13:09           ` Jason Gunthorpe
2023-11-09 13:52             ` Vasant Hegde
2023-11-09 14:10               ` Jason Gunthorpe
2023-11-10  5:28                 ` Vasant Hegde
2023-11-10 14:02                   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 11/13] iommu/amd/pgtbl_v2: Invalidate updated page ranges only Vasant Hegde
2023-11-05 17:57   ` Jason Gunthorpe
2023-11-06 11:16     ` Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 12/13] iommu/amd: Remove unused flush pasid functions Vasant Hegde
2023-11-05 17:58   ` Jason Gunthorpe
2023-11-06 11:19     ` Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 13/13] iommu/amd: Rearrange device flush code Vasant Hegde
2023-11-05 17:59   ` Jason Gunthorpe
2023-11-06 11:45     ` Vasant Hegde
2023-10-12  6:17 ` [PATCH v1 00/13] Improve TLB invalidation logic Suthikulpanit, Suravee
2023-10-16 10:18 ` Vasant Hegde

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