From: Vasant Hegde <vasant.hegde@amd.com>
To: <iommu@lists.linux.dev>, <joro@8bytes.org>
Cc: <suravee.suthikulpanit@amd.com>, <wei.huang2@amd.com>,
<jsnitsel@redhat.com>, <jgg@ziepe.ca>,
Vasant Hegde <vasant.hegde@amd.com>
Subject: [PATCH v4 02/14] iommu/amd: Introduce per device DTE update function
Date: Thu, 21 Dec 2023 11:15:46 +0000 [thread overview]
Message-ID: <20231221111558.64652-3-vasant.hegde@amd.com> (raw)
In-Reply-To: <20231221111558.64652-1-vasant.hegde@amd.com>
Consolidate per device update and flush logic into separate function.
Also make it as global function as it will be used in subsequent series
to update the DTE.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
---
drivers/iommu/amd/amd_iommu.h | 1 +
drivers/iommu/amd/iommu.c | 26 ++++++++++++++++++--------
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index 2f6fba75e0ee..e8ac7826a14c 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -64,6 +64,7 @@ int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid);
void amd_iommu_flush_all_caches(struct amd_iommu *iommu);
void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
void amd_iommu_domain_update(struct protection_domain *domain);
+void amd_iommu_dev_update_dte(struct iommu_dev_data *dev_data, bool set);
void amd_iommu_domain_flush_complete(struct protection_domain *domain);
void amd_iommu_domain_flush_pages(struct protection_domain *domain,
u64 address, size_t size);
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index d9050855496a..fe08b4cf446f 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2025,6 +2025,21 @@ static void clear_dte_entry(struct amd_iommu *iommu, u16 devid)
amd_iommu_apply_erratum_63(iommu, devid);
}
+/* Update and flush DTE for the given device */
+void amd_iommu_dev_update_dte(struct iommu_dev_data *dev_data, bool set)
+{
+ struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev);
+
+ if (set)
+ set_dte_entry(iommu, dev_data);
+ else
+ clear_dte_entry(iommu, dev_data->devid);
+
+ clone_aliases(iommu, dev_data->dev);
+
+ device_flush_dte(dev_data);
+}
+
static int do_attach(struct iommu_dev_data *dev_data,
struct protection_domain *domain)
{
@@ -2068,10 +2083,7 @@ static int do_attach(struct iommu_dev_data *dev_data,
}
/* Update device table */
- set_dte_entry(iommu, dev_data);
- clone_aliases(iommu, dev_data->dev);
-
- device_flush_dte(dev_data);
+ amd_iommu_dev_update_dte(dev_data, true);
return ret;
}
@@ -2092,11 +2104,9 @@ static void do_detach(struct iommu_dev_data *dev_data)
/* Update data structures */
dev_data->domain = NULL;
list_del(&dev_data->list);
- clear_dte_entry(iommu, dev_data->devid);
- clone_aliases(iommu, dev_data->dev);
- /* Flush the DTE entry */
- device_flush_dte(dev_data);
+ /* Clear DTE and flush the entry */
+ amd_iommu_dev_update_dte(dev_data, false);
/* Flush IOTLB and wait for the flushes to finish */
amd_iommu_domain_flush_all(domain);
--
2.31.1
next prev parent reply other threads:[~2023-12-21 11:16 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-21 11:15 [PATCH v4 00/14] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 01/14] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() Vasant Hegde
2023-12-21 11:15 ` Vasant Hegde [this message]
2023-12-21 11:15 ` [PATCH v4 03/14] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 04/14] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 05/14] iommu/amd: Fix PPR interrupt processing logic Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 06/14] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 07/14] iommu/amd: Add support for page response Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 08/14] iommu/amd: Add support for add/remove device for IOPF Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 09/14] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 10/14] iommu/amd: Introduce logic to enable/disable IOPF Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 11/14] iommu/amd: Add GCR3 [un]initialization function Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 12/14] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 13/14] iommu: Add ops->domain_alloc_sva() Vasant Hegde
2024-01-08 6:46 ` Tina Zhang
2024-01-09 17:50 ` Jason Gunthorpe
2024-01-11 5:18 ` Vasant Hegde
2023-12-21 11:15 ` [PATCH v4 14/14] iommu/amd: Add SVA domain support Vasant Hegde
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231221111558.64652-3-vasant.hegde@amd.com \
--to=vasant.hegde@amd.com \
--cc=iommu@lists.linux.dev \
--cc=jgg@ziepe.ca \
--cc=joro@8bytes.org \
--cc=jsnitsel@redhat.com \
--cc=suravee.suthikulpanit@amd.com \
--cc=wei.huang2@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox