From: Vasant Hegde <vasant.hegde@amd.com>
To: <iommu@lists.linux.dev>, <joro@8bytes.org>
Cc: <suravee.suthikulpanit@amd.com>, <wei.huang2@amd.com>,
<jsnitsel@redhat.com>, <jgg@ziepe.ca>,
Vasant Hegde <vasant.hegde@amd.com>
Subject: [PATCH v6 12/15] iommu/amd: Add support for enable/disable IOPF
Date: Fri, 9 Feb 2024 11:29:27 +0000 [thread overview]
Message-ID: <20240209112930.63663-13-vasant.hegde@amd.com> (raw)
In-Reply-To: <20240209112930.63663-1-vasant.hegde@amd.com>
Return success from enable_feature(IOPF) path as this interface is going
away. Instead we will enable/disable IOPF support in attach/detach device
path.
In attach device path, if device is capable of PRI, then we will add it to
per IOMMU IOPF queue and enable PPR support in IOMMU. Also it will
attach device to domain even if it fails to enable PRI or add device to
IOPF queue as device can continue to work without PRI support.
In detach device patch it follows following sequence:
- Flush the queue for the given device
- Disable PPR support in DTE[devid]
- Remove device from IOPF queue
- Disable device PRI
Also add IOMMU_IOPF as dependency to AMD_IOMMU driver.
Co-developed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
---
drivers/iommu/amd/Kconfig | 1 +
drivers/iommu/amd/amd_iommu.h | 4 ++++
drivers/iommu/amd/iommu.c | 40 +++++++++++++++++++++++++++-------
drivers/iommu/amd/ppr.c | 41 +++++++++++++++++++++++++++++++++++
4 files changed, 78 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/amd/Kconfig b/drivers/iommu/amd/Kconfig
index 443b2c13c37b..d563f6d496ca 100644
--- a/drivers/iommu/amd/Kconfig
+++ b/drivers/iommu/amd/Kconfig
@@ -10,6 +10,7 @@ config AMD_IOMMU
select IOMMU_API
select IOMMU_IOVA
select IOMMU_IO_PGTABLE
+ select IOMMU_IOPF
select IOMMUFD_DRIVER if IOMMUFD
depends on X86_64 && PCI && ACPI && HAVE_CMPXCHG_DOUBLE
help
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index 030a04451599..384298206a2d 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -51,6 +51,10 @@ int amd_iommu_iopf_init(struct amd_iommu *iommu);
void amd_iommu_iopf_uninit(struct amd_iommu *iommu);
void amd_iommu_page_response(struct device *dev, struct iopf_fault *evt,
struct iommu_page_response *resp);
+int amd_iommu_iopf_add_device(struct amd_iommu *iommu,
+ struct iommu_dev_data *dev_data);
+void amd_iommu_iopf_remove_device(struct amd_iommu *iommu,
+ struct iommu_dev_data *dev_data);
struct amd_iommu *get_amd_iommu(unsigned int idx);
u8 amd_iommu_pc_get_max_banks(unsigned int idx);
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 0fa172e0583d..21cc6654410f 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2058,12 +2058,22 @@ static int do_attach(struct iommu_dev_data *dev_data,
if (ret)
return ret;
- if (pdev)
+ if (pdev) {
pdev_enable_caps(pdev);
+
+ /*
+ * Device can continue to function even if IOPF
+ * enablement failed. Hence in error path just
+ * disable device PRI support.
+ */
+ if (amd_iommu_iopf_add_device(iommu, dev_data))
+ pdev_disable_cap_pri(pdev);
+ }
} else if (pdev) {
pdev_enable_cap_ats(pdev);
}
+
/* Update device table */
amd_iommu_dev_update_dte(dev_data, true);
@@ -2131,12 +2141,11 @@ static int attach_device(struct device *dev,
*/
static void detach_device(struct device *dev)
{
- struct protection_domain *domain;
- struct iommu_dev_data *dev_data;
+ struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
+ struct protection_domain *domain = dev_data->domain;
+ struct amd_iommu *iommu = get_amd_iommu_from_dev_data(dev_data);
unsigned long flags;
-
- dev_data = dev_iommu_priv_get(dev);
- domain = dev_data->domain;
+ bool ppr = dev_data->ppr;
spin_lock_irqsave(&domain->lock, flags);
@@ -2151,8 +2160,19 @@ static void detach_device(struct device *dev)
if (WARN_ON(!dev_data->domain))
goto out;
+ if (ppr) {
+ iopf_queue_flush_dev(dev);
+
+ /* Updated here so that it gets reflected in DTE */
+ dev_data->ppr = false;
+ }
+
do_detach(dev_data);
+ /* Remove IOPF handler */
+ if (ppr)
+ amd_iommu_iopf_remove_device(iommu, dev_data);
+
if (dev_is_pci(dev))
pdev_disable_caps(to_pci_dev(dev));
@@ -2816,9 +2836,11 @@ static const struct iommu_dirty_ops amd_dirty_ops = {
static int amd_iommu_dev_enable_feature(struct device *dev,
enum iommu_dev_features feat)
{
- int ret;
+ int ret = 0;
switch (feat) {
+ case IOMMU_DEV_FEAT_IOPF:
+ break;
default:
ret = -EINVAL;
break;
@@ -2829,9 +2851,11 @@ static int amd_iommu_dev_enable_feature(struct device *dev,
static int amd_iommu_dev_disable_feature(struct device *dev,
enum iommu_dev_features feat)
{
- int ret;
+ int ret = 0;
switch (feat) {
+ case IOMMU_DEV_FEAT_IOPF:
+ break;
default:
ret = -EINVAL;
break;
diff --git a/drivers/iommu/amd/ppr.c b/drivers/iommu/amd/ppr.c
index 46d0ad13ac08..dca4bf7f704e 100644
--- a/drivers/iommu/amd/ppr.c
+++ b/drivers/iommu/amd/ppr.c
@@ -241,3 +241,44 @@ void amd_iommu_page_response(struct device *dev, struct iopf_fault *evt,
{
amd_iommu_complete_ppr(dev, resp->pasid, resp->code, resp->grpid);
}
+
+int amd_iommu_iopf_add_device(struct amd_iommu *iommu,
+ struct iommu_dev_data *dev_data)
+{
+ unsigned long flags;
+ int ret = 0;
+
+ if (!dev_data->pri_enabled)
+ return ret;
+
+ raw_spin_lock_irqsave(&iommu->lock, flags);
+
+ if (!iommu->iopf_queue) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+
+ ret = iopf_queue_add_device(iommu->iopf_queue, dev_data->dev);
+ if (ret)
+ goto out_unlock;
+
+ dev_data->ppr = true;
+
+out_unlock:
+ raw_spin_unlock_irqrestore(&iommu->lock, flags);
+ return ret;
+}
+
+/* Its assumed that caller has verified that device was added to iopf queue */
+void amd_iommu_iopf_remove_device(struct amd_iommu *iommu,
+ struct iommu_dev_data *dev_data)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&iommu->lock, flags);
+
+ iopf_queue_remove_device(iommu->iopf_queue, dev_data->dev);
+ dev_data->ppr = false;
+
+ raw_spin_unlock_irqrestore(&iommu->lock, flags);
+}
--
2.31.1
next prev parent reply other threads:[~2024-02-09 11:34 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-09 11:29 [PATCH v6 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 01/15] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 02/15] iommu/amd: Introduce per device DTE update function Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 03/15] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 04/15] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 05/15] iommu/amd: Fix PPR interrupt processing logic Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 06/15] iommu/amd: Introduce iommu_dev_data.max_pasids Vasant Hegde
2024-03-04 23:46 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 07/15] iommu/amd: Setup GCR3 table in advance if domain is SVA capable Vasant Hegde
2024-03-05 0:11 ` Jason Gunthorpe
2024-03-11 11:20 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 08/15] iommu/amd: Enable PCI features based on attached domain capability Vasant Hegde
2024-03-05 0:32 ` Jason Gunthorpe
2024-03-05 15:10 ` Vasant Hegde
2024-03-05 16:01 ` Jason Gunthorpe
2024-03-11 10:02 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 09/15] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2024-03-05 0:33 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 10/15] iommu/amd: Add support for page response Vasant Hegde
2024-03-05 0:35 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 11/15] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2024-03-05 0:40 ` Jason Gunthorpe
2024-03-11 11:00 ` Vasant Hegde
2024-03-19 17:54 ` Jason Gunthorpe
2024-02-09 11:29 ` Vasant Hegde [this message]
2024-03-05 0:42 ` [PATCH v6 12/15] iommu/amd: Add support for enable/disable IOPF Jason Gunthorpe
2024-03-05 15:21 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 13/15] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2024-03-05 0:50 ` Jason Gunthorpe
2024-03-11 11:11 ` Vasant Hegde
2024-03-19 17:56 ` Jason Gunthorpe
2024-03-27 6:15 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 14/15] iommu: Add ops->domain_alloc_sva() Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 15/15] iommu/amd: Add SVA domain support Vasant Hegde
2024-03-05 0:52 ` [PATCH v6 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF Jason Gunthorpe
2024-03-05 14:59 ` Vasant Hegde
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240209112930.63663-13-vasant.hegde@amd.com \
--to=vasant.hegde@amd.com \
--cc=iommu@lists.linux.dev \
--cc=jgg@ziepe.ca \
--cc=joro@8bytes.org \
--cc=jsnitsel@redhat.com \
--cc=suravee.suthikulpanit@amd.com \
--cc=wei.huang2@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox