From: Jason Gunthorpe <jgg@ziepe.ca>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org,
suravee.suthikulpanit@amd.com, wei.huang2@amd.com,
jsnitsel@redhat.com
Subject: Re: [PATCH v6 11/15] iommu/amd: Add IO page fault notifier handler
Date: Mon, 4 Mar 2024 20:40:01 -0400 [thread overview]
Message-ID: <20240305004001.GF9225@ziepe.ca> (raw)
In-Reply-To: <20240209112930.63663-12-vasant.hegde@amd.com>
On Fri, Feb 09, 2024 at 11:29:26AM +0000, Vasant Hegde wrote:
> +static bool ppr_is_valid(struct amd_iommu *iommu, u64 *raw)
> +{
> + struct device *dev = iommu->iommu.dev;
> + u16 devid = PPR_DEVID(raw[0]);
> +
> + if (!(PPR_FLAGS(raw[0]) & PPR_FLAG_GN)) {
> + dev_dbg(dev, "PPR logged [Request ignored due to GN=0 (device=%04x:%02x:%02x.%x "
> + "pasid=0x%05llx address=0x%llx flags=0x%04llx tag=0x%03llx]\n",
> + iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
> + PPR_PASID(raw[0]), raw[1], PPR_FLAGS(raw[0]), PPR_TAG(raw[0]));
> + return false;
Someday this will not be an error..
> +static void iommu_call_iopf_notifier(struct amd_iommu *iommu, u64 *raw)
> +{
> + struct iommu_dev_data *dev_data;
> + struct iopf_fault event;
> + struct pci_dev *pdev;
> + u16 devid = PPR_DEVID(raw[0]);
> +
> + if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
> + pr_info_ratelimited("Unknown PPR request received\n");
> + return;
> + }
> +
> + pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id,
> + PCI_BUS_NUM(devid), devid & 0xff);
> + if (!pdev)
> + return;
> +
> + if (!ppr_is_valid(iommu, raw))
> + goto out;
> +
> + memset(&event, 0, sizeof(struct iopf_fault));
> +
> + event.fault.type = IOMMU_FAULT_PAGE_REQ;
> + event.fault.prm.perm = ppr_flag_to_fault_perm(PPR_FLAGS(raw[0]));
> + event.fault.prm.addr = (u64)(raw[1] & PAGE_MASK);
> + event.fault.prm.pasid = PPR_PASID(raw[0]);
> + event.fault.prm.grpid = PPR_TAG(raw[0]) & 0x1FF;
> +
> + /*
> + * PASID zero is used for requests from the I/O device without
> + * a PASID
> + */
> + dev_data = dev_iommu_priv_get(&pdev->dev);
> + if (event.fault.prm.pasid == 0 ||
> + event.fault.prm.pasid >= dev_data->max_pasids) {
> + pr_info_ratelimited("Invalid PASID : 0x%x, device : 0x%x\n",
> + event.fault.prm.pasid, pdev->dev.id);
> + goto out;
> + }
Why even do this check? The core code is perfectly fine to take in a
big pasid value, it will not match anything in the xarray and just be
completed with error anyhow.
Looks fine otherwise
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Jason
next prev parent reply other threads:[~2024-03-05 0:40 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-09 11:29 [PATCH v6 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 01/15] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 02/15] iommu/amd: Introduce per device DTE update function Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 03/15] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 04/15] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 05/15] iommu/amd: Fix PPR interrupt processing logic Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 06/15] iommu/amd: Introduce iommu_dev_data.max_pasids Vasant Hegde
2024-03-04 23:46 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 07/15] iommu/amd: Setup GCR3 table in advance if domain is SVA capable Vasant Hegde
2024-03-05 0:11 ` Jason Gunthorpe
2024-03-11 11:20 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 08/15] iommu/amd: Enable PCI features based on attached domain capability Vasant Hegde
2024-03-05 0:32 ` Jason Gunthorpe
2024-03-05 15:10 ` Vasant Hegde
2024-03-05 16:01 ` Jason Gunthorpe
2024-03-11 10:02 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 09/15] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2024-03-05 0:33 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 10/15] iommu/amd: Add support for page response Vasant Hegde
2024-03-05 0:35 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 11/15] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2024-03-05 0:40 ` Jason Gunthorpe [this message]
2024-03-11 11:00 ` Vasant Hegde
2024-03-19 17:54 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 12/15] iommu/amd: Add support for enable/disable IOPF Vasant Hegde
2024-03-05 0:42 ` Jason Gunthorpe
2024-03-05 15:21 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 13/15] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2024-03-05 0:50 ` Jason Gunthorpe
2024-03-11 11:11 ` Vasant Hegde
2024-03-19 17:56 ` Jason Gunthorpe
2024-03-27 6:15 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 14/15] iommu: Add ops->domain_alloc_sva() Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 15/15] iommu/amd: Add SVA domain support Vasant Hegde
2024-03-05 0:52 ` [PATCH v6 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF Jason Gunthorpe
2024-03-05 14:59 ` Vasant Hegde
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240305004001.GF9225@ziepe.ca \
--to=jgg@ziepe.ca \
--cc=iommu@lists.linux.dev \
--cc=joro@8bytes.org \
--cc=jsnitsel@redhat.com \
--cc=suravee.suthikulpanit@amd.com \
--cc=vasant.hegde@amd.com \
--cc=wei.huang2@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox