[PATCH v2 0/2] iommu/vt-d: Fix aligned pages for cache invalidation

[PATCH v2 0/2] iommu/vt-d: Fix aligned pages for cache invalidation

[Lu Baolu]

The aligned pages for cache invalidation returned by
calculate_psi_aligned_address() are incorrect if the start pfn is not
aligned, which can lead to cache inconsistencies when qi_flush_piotlb()
uses the number of pages to flush caches for the first-stage
translation.

Fix this by updating the aligned pages once the address mask is adjusted.

Change log:

v2:
 - Add a new fix to Limit max address mask to MAX_AGAW_PFN_WIDTH.

v1: https://lore.kernel.org/linux-iommu/20240708121417.18705-1-baolu.lu@linux.intel.com/

Lu Baolu (2):
  iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH
  iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()

 drivers/iommu/intel/cache.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

-- 
2.34.1

[PATCH v2 1/2] iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH

[Lu Baolu]

Address mask specifies the number of low order bits of the address field
that must be masked for the invalidation operation.

Since address bits masked start from bit 12, the max address mask should
be MAX_AGAW_PFN_WIDTH, as defined in Table 19 ("Invalidate Descriptor
Address Mask Encodings") of the spec.

Limit the max address mask returned from calculate_psi_aligned_address()
to MAX_AGAW_PFN_WIDTH to prevent potential integer overflow in the
following code:

qi_flush_dev_iotlb():
    ...
    addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
    ...

Fixes: c4d27ffaa8eb ("iommu/vt-d: Add cache tag invalidation helpers")
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
---
 drivers/iommu/intel/cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c
index e8418cdd8331..0a3bb38a5289 100644
--- a/drivers/iommu/intel/cache.c
+++ b/drivers/iommu/intel/cache.c
@@ -245,7 +245,7 @@ static unsigned long calculate_psi_aligned_address(unsigned long start,
 		 * shared_bits are all equal in both pfn and end_pfn.
 		 */
 		shared_bits = ~(pfn ^ end_pfn) & ~bitmask;
-		mask = shared_bits ? __ffs(shared_bits) : BITS_PER_LONG;
+		mask = shared_bits ? __ffs(shared_bits) : MAX_AGAW_PFN_WIDTH;
 	}
 
 	*_pages = aligned_pages;
-- 
2.34.1

[PATCH v2 2/2] iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()

[Lu Baolu]

The helper calculate_psi_aligned_address() is used to convert an arbitrary
range into a size-aligned one.

The aligned_pages variable is calculated from input start and end, but is
not adjusted when the start pfn is not aligned and the mask is adjusted,
which results in an incorrect number of pages returned.

The number of pages is used by qi_flush_piotlb() to flush caches for the
first-stage translation. With the wrong number of pages, the cache is not
synchronized, leading to inconsistencies in some cases.

Fixes: c4d27ffaa8eb ("iommu/vt-d: Add cache tag invalidation helpers")
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
---
 drivers/iommu/intel/cache.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c
index 0a3bb38a5289..44e92638c0cd 100644
--- a/drivers/iommu/intel/cache.c
+++ b/drivers/iommu/intel/cache.c
@@ -246,6 +246,7 @@ static unsigned long calculate_psi_aligned_address(unsigned long start,
 		 */
 		shared_bits = ~(pfn ^ end_pfn) & ~bitmask;
 		mask = shared_bits ? __ffs(shared_bits) : MAX_AGAW_PFN_WIDTH;
+		aligned_pages = 1UL << mask;
 	}
 
 	*_pages = aligned_pages;
-- 
2.34.1

Re: [PATCH v2 0/2] iommu/vt-d: Fix aligned pages for cache invalidation

[Will Deacon]

On Tue, 09 Jul 2024 23:26:41 +0800, Lu Baolu wrote:
> The aligned pages for cache invalidation returned by
> calculate_psi_aligned_address() are incorrect if the start pfn is not
> aligned, which can lead to cache inconsistencies when qi_flush_piotlb()
> uses the number of pages to flush caches for the first-stage
> translation.
> 
> Fix this by updating the aligned pages once the address mask is adjusted.
> 
> [...]

Applied to iommu (intel/vt-d), thanks!

[1/2] iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH
      https://git.kernel.org/iommu/c/c420a2b4e8be
[2/2] iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()
      https://git.kernel.org/iommu/c/0a3f6b346301

Cheers,
-- 
Will

https://fixes.arm64.dev
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