[PATCH 1/3] dt-bindings: iommu: add "arm,smmu-pci-msi-iova-data" property

[Shyam Saini <shyamsaini@linux.microsoft.com>]

By default ARM SMMU drivers use MSI_IOVA_BASE macro to reserve
PCI MSI IOVA memory range, this assumes that all the platforms have
MSI_IOVA_BASE address available for MSI reservation. However, this
is not always the case, as some platforms may have the default
address reserved for some other purposes and as a consequence ARM SMMU
drivers can't reserve MSI memory for those platforms.

To address this issue, add a new dts property
"arm,smmu-pci-msi-iova-data" which can be used to hold custom
PCI MSI IOVA address and its address length. This property can be passed
to ARM SMMU drivers via device tree to reserve specified memory range
for MSI.

Signed-off-by: Shyam Saini <shyamsaini@linux.microsoft.com>
---
 .../devicetree/bindings/iommu/arm,smmu-v3.yaml       | 12 ++++++++++++
 .../devicetree/bindings/iommu/arm,smmu.yaml          | 12 ++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index 75fcf4cb52d9f..dbad612886604 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -56,6 +56,17 @@ properties:
       NOTE: this only applies to the SMMU itself, not masters connected
       upstream of the SMMU.
 
+  arm,smmu-pci-msi-iova-data:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      Specifies a custom PCI MSI base I/O Virtual Address and its memory range
+      size for ARM SMMU drivers. This allows setting a custom address and
+      memory size pair if the default MSI_IOVA_BASE_DEFAULT address and
+      MSI_IOVA_LENGTH_DEFAULT size are not suitable for the intended platform.
+    items:
+      - description: MSI IOVA base address
+      - description: MSI IOVA address length
+
   msi-parent: true
 
   hisilicon,broken-prefetch-cmd:
@@ -92,4 +103,5 @@ examples:
             dma-coherent;
             #iommu-cells = <1>;
             msi-parent = <&its 0xff0000>;
+            arm,smmu-pci-msi-iova-data = <0xa0000000 0x100000>;
     };
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 032fdc27127bf..d080b13765d1f 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -207,6 +207,17 @@ properties:
       NOTE: this only applies to the SMMU itself, not masters connected
       upstream of the SMMU.
 
+  arm,smmu-pci-msi-iova-data:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      Specifies a custom PCI MSI base I/O Virtual Address and its memory range
+      size for ARM SMMU drivers. This allows setting a custom address and
+      memory size pair if the default MSI_IOVA_BASE_DEFAULT address and
+      MSI_IOVA_LENGTH_DEFAULT size are not suitable for the intended platform.
+    items:
+      - description: MSI IOVA base address
+      - description: MSI IOVA address length
+
   calxeda,smmu-secure-config-access:
     type: boolean
     description:
@@ -679,6 +690,7 @@ examples:
             #iommu-cells = <1>;
             /* always ignore appended 5-bit TBU number */
             stream-match-mask = <0x7c00>;
+            arm,smmu-pci-msi-iova-data = <0xa0000000 0x100000>;
     };
 
     bus {
-- 
2.34.1