Re: REGRESSION on linux-next (next-20251106)

[Jason Gunthorpe <jgg@nvidia.com>]

On Wed, Nov 19, 2025 at 11:56:16PM +0000, Tian, Kevin wrote:
> > So we should be using dmar->width to constrain the first stage and
> > expect that mgaw is less than dmar->width ?
> > 
> 
> dmar->width is the host address width, i.e. for OA. so it's irrelevant
> to the input iova here.

Oh that makes sense!

In that case we should probably pedantically have:

	cfg.common.hw_max_oasz_lg2 = dmar->width;

?

However we get dmar into that function?

> "
> 3.6 First-Stage Translation
> 
> First-stage translation restricts the input-address to a canonical address
> (i.e., address bits 63:N have the same value as address bit [N-1], where
> N is 48 bits with 4-level paging and 57 bits with 5-level paging). Requests
> subject to first-stage translation by remapping hardware are subject to
> canonical address checking as a pre-condition for first-stage translation, 
> and a violation is treated as a translation-fault.
> 
> Software using first-stage translation structures to translate an IO Virtual
> Address (IOVA) must use canonical addresses. Additionally, software
> must limit addresses to less than the minimum of MGAW and the lower
> canonical address width implied by FSPM (i.e., 47-bit when FSPM is 4-level
> and 56-bit when FSPM is 5-level)
> "

That seems very clear, indeed. OK! Easy to fix then! Balou can you
take it? I think something like this?

@@ -2800,6 +2800,7 @@ intel_iommu_domain_alloc_first_stage(struct device *dev,
 {
+       unsigned int mgaw = cap_mgaw(iommu->cap);
        struct pt_iommu_x86_64_cfg cfg = {};
        struct dmar_domain *dmar_domain;
        int ret;
 
        if (flags & ~IOMMU_HWPT_ALLOC_PASID)
@@ -2817,7 +2818,12 @@ intel_iommu_domain_alloc_first_stage(struct device *dev,
                cfg.common.hw_max_vasz_lg2 = 57;
        else
                cfg.common.hw_max_vasz_lg2 = 48;
+
+       /*
+        * See "3.6 First-Stage Translation", mgaw is used to limit the first
+        * stage as well.
+        */
+       cfg.common.hw_max_vasz_lg2 = min(mgaw, cfg.common.hw_max_vasz_lg2);
        cfg.common.hw_max_oasz_lg2 = 52;
        cfg.common.features = BIT(PT_FEAT_FLUSH_RANGE);
        /* First stage always uses scalable mode */
@@ -3004,6 +3010,11 @@ static int paging_domain_compatible_first_stage(struct dmar_domain *dmar_domain,
            dmar_domain->fspt.x86_64_pt.common.max_vasz_lg2 > 48)
                return -EINVAL;
 
+       /* Address bits have to be identical to HW because of the sign extension */
+       if (dmar_domain->fspt.x86_64_pt.common.max_vasz_lg2 !=
+           cap_mgaw(iommu->cap))
+               return -EINVAL;
+
        /* Same page size support */
        if (!cap_fl1gp_support(iommu->cap) &&
            (dmar_domain->domain.pgsize_bitmap & SZ_1G))

Jason