From: Baolu Lu <baolu.lu@linux.intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>,
"Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>
Cc: baolu.lu@linux.intel.com,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
Lucas De Marchi <lucas.demarchi@intel.com>,
"Kurmi, Suresh Kumar" <suresh.kumar.kurmi@intel.com>,
"Saarinen, Jani" <jani.saarinen@intel.com>,
matthew.auld@intel.com, iommu@lists.linux.dev
Subject: Re: REGRESSION on linux-next (next-20251106)
Date: Wed, 19 Nov 2025 17:29:21 +0800 [thread overview]
Message-ID: <8648735e-324d-4951-96a8-6276503fc8c9@linux.intel.com> (raw)
In-Reply-To: <20251118161341.GC90703@nvidia.com>
On 11/19/2025 12:13 AM, Jason Gunthorpe wrote:
>> Also, the tests fail consistently and are not sporadic.
> From these logs I see the below fragment, noting this:
>
> gem_exec_gttfil-1010 [004] .N... 50.126420: map: IOMMU: iova=0x00003fffffc00000 - 0x0000400000000000 paddr=0x00000001b9400000 size=4194304
> ^^^^^^^^^^^^^^^^^^^
> Which is the high IOVA.. It has bit 45 set. I fed this mapping into
> the kunit and it does map successfully.
>
> It is not high enough to get into anything special about sign extend,
> the driver sets:
>
> if (cap_fl5lp_support(iommu->cap))
> cfg.common.hw_max_vasz_lg2 = 57;
> else
> cfg.common.hw_max_vasz_lg2 = 48;
>
> Maybe this code is wrong? Baolu what did you get for this log:
>
> [ 50.126166] i915 0000:00:02.0: Using 46-bit DMA addresses
>
> In your force second stage test? Is it 46? Second stage uses different
> code to compute vasz_lg2 and is sensitive to magw:
>
> if (mgaw >= 48 && (sagaw & BIT(3)))
> return min(57, mgaw);
> else if (mgaw >= 39 && (sagaw & BIT(2)))
> return min(48, mgaw);
> else if (mgaw >= 30 && (sagaw & BIT(1)))
> return min(39, mgaw);
>
> Maybe this is the issue?
When first stage translation is used,
cfg.common.hw_max_vasz_lg2 = 48
When second stage translation is used,
cfg.common.hw_max_vasz_lg2 = 42
Interesting thing is if I hardcode
cfg.common.hw_max_vasz_lg2 = 42
for the first stage translation, it works.
The only change that I have made to achieve this likes below:
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 2d2f64ce2bc6..a505bba8dcc7 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -2813,10 +2813,13 @@ intel_iommu_domain_alloc_first_stage(struct
device *dev,
if (IS_ERR(dmar_domain))
return ERR_CAST(dmar_domain);
+#if 0
if (cap_fl5lp_support(iommu->cap))
cfg.common.hw_max_vasz_lg2 = 57;
else
cfg.common.hw_max_vasz_lg2 = 48;
+#endif
+ cfg.common.hw_max_vasz_lg2 = 42;
cfg.common.hw_max_oasz_lg2 = 52;
cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) |
BIT(PT_FEAT_FLUSH_RANGE);
Thanks,
baolu
prev parent reply other threads:[~2025-11-19 9:29 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-10 6:36 REGRESSION on linux-next (next-20251106) Borah, Chaitanya Kumar
2025-11-12 22:32 ` Jason Gunthorpe
2025-11-13 2:00 ` Tian, Kevin
2025-11-17 15:24 ` Jason Gunthorpe
2025-11-17 12:54 ` Baolu Lu
2025-11-17 15:22 ` Jason Gunthorpe
2025-11-18 1:29 ` Jason Gunthorpe
2025-11-18 4:04 ` Tian, Kevin
2025-11-18 6:19 ` Baolu Lu
2025-11-18 6:23 ` Baolu Lu
2025-11-18 7:47 ` Tian, Kevin
2025-11-18 11:29 ` Baolu Lu
2025-11-18 12:35 ` Jason Gunthorpe
2025-11-19 7:25 ` Baolu Lu
2025-11-18 10:30 ` Baolu Lu
2025-11-18 15:16 ` Borah, Chaitanya Kumar
2025-11-18 16:13 ` Jason Gunthorpe
2025-11-19 7:40 ` Borah, Chaitanya Kumar
2025-11-19 9:31 ` Tian, Kevin
2025-11-19 18:51 ` Jason Gunthorpe
2025-11-19 23:56 ` Tian, Kevin
2025-11-20 2:18 ` Jason Gunthorpe
2025-11-20 2:24 ` Baolu Lu
2025-11-20 7:27 ` Baolu Lu
2025-11-20 0:19 ` Tian, Kevin
2025-11-19 9:29 ` Baolu Lu [this message]
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