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* [PATCH v2] iommu/vt-d: Flush piotlb for SVM and Nested domain
@ 2025-12-23  6:58 Yi Liu
  2026-01-06  7:56 ` Tian, Kevin
  2026-01-20  7:09 ` Baolu Lu
  0 siblings, 2 replies; 3+ messages in thread
From: Yi Liu @ 2025-12-23  6:58 UTC (permalink / raw)
  To: kevin.tian, baolu.lu; +Cc: joro, yi.l.liu, iommu, jgg

Besides the paging domains that use FS, SVM and Nested domains need to
use piotlb invalidation descriptor as well.

Fixes: b33125296b50 ("iommu/vt-d: Create unique domain ops for each stage")
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
---
Change log:
v2:
- Use domain.type to filter nested and SVA type domain. This eliminates
  the SVA domain ops reference issue when SVM is compiled out. (Kevin)
- Add a intel_domain_use_piotlb() helper to cover the three cases which
  need to flush piotlb. (Kevin)

v1: https://lore.kernel.org/linux-iommu/20251208091907.74719-1-yi.l.liu@intel.com/
---
 drivers/iommu/intel/cache.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c
index 265e7290256b..385ae5cfb30d 100644
--- a/drivers/iommu/intel/cache.c
+++ b/drivers/iommu/intel/cache.c
@@ -363,6 +363,13 @@ static void qi_batch_add_pasid_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16
 	qi_batch_increment_index(iommu, batch);
 }
 
+static bool intel_domain_use_piotlb(struct dmar_domain *domain)
+{
+	return domain->domain.type == IOMMU_DOMAIN_SVA ||
+			domain->domain.type == IOMMU_DOMAIN_NESTED ||
+			intel_domain_is_fs_paging(domain);
+}
+
 static void cache_tag_flush_iotlb(struct dmar_domain *domain, struct cache_tag *tag,
 				  unsigned long addr, unsigned long pages,
 				  unsigned long mask, int ih)
@@ -370,7 +377,7 @@ static void cache_tag_flush_iotlb(struct dmar_domain *domain, struct cache_tag *
 	struct intel_iommu *iommu = tag->iommu;
 	u64 type = DMA_TLB_PSI_FLUSH;
 
-	if (intel_domain_is_fs_paging(domain)) {
+	if (intel_domain_use_piotlb(domain)) {
 		qi_batch_add_piotlb(iommu, tag->domain_id, tag->pasid, addr,
 				    pages, ih, domain->qi_batch);
 		return;
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* RE: [PATCH v2] iommu/vt-d: Flush piotlb for SVM and Nested domain
  2025-12-23  6:58 [PATCH v2] iommu/vt-d: Flush piotlb for SVM and Nested domain Yi Liu
@ 2026-01-06  7:56 ` Tian, Kevin
  2026-01-20  7:09 ` Baolu Lu
  1 sibling, 0 replies; 3+ messages in thread
From: Tian, Kevin @ 2026-01-06  7:56 UTC (permalink / raw)
  To: Liu, Yi L, baolu.lu@linux.intel.com
  Cc: joro@8bytes.org, iommu@lists.linux.dev, jgg@nvidia.com

> From: Liu, Yi L <yi.l.liu@intel.com>
> Sent: Tuesday, December 23, 2025 2:58 PM
> 
> Besides the paging domains that use FS, SVM and Nested domains need to
> use piotlb invalidation descriptor as well.
> 
> Fixes: b33125296b50 ("iommu/vt-d: Create unique domain ops for each
> stage")
> Signed-off-by: Yi Liu <yi.l.liu@intel.com>

cc stable

> ---
> Change log:
> v2:
> - Use domain.type to filter nested and SVA type domain. This eliminates
>   the SVA domain ops reference issue when SVM is compiled out. (Kevin)
> - Add a intel_domain_use_piotlb() helper to cover the three cases which
>   need to flush piotlb. (Kevin)
> 
> v1: https://lore.kernel.org/linux-iommu/20251208091907.74719-1-
> yi.l.liu@intel.com/
> ---
>  drivers/iommu/intel/cache.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c
> index 265e7290256b..385ae5cfb30d 100644
> --- a/drivers/iommu/intel/cache.c
> +++ b/drivers/iommu/intel/cache.c
> @@ -363,6 +363,13 @@ static void qi_batch_add_pasid_dev_iotlb(struct
> intel_iommu *iommu, u16 sid, u16
>  	qi_batch_increment_index(iommu, batch);
>  }
> 
> +static bool intel_domain_use_piotlb(struct dmar_domain *domain)
> +{
> +	return domain->domain.type == IOMMU_DOMAIN_SVA ||
> +			domain->domain.type == IOMMU_DOMAIN_NESTED
> ||
> +			intel_domain_is_fs_paging(domain);

for readability:
	intel_domain_is_sva()
	intel_domain_is_nested()

otherwise,

Reviewed-by: Kevin Tian <kevin.tian@intel.com>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] iommu/vt-d: Flush piotlb for SVM and Nested domain
  2025-12-23  6:58 [PATCH v2] iommu/vt-d: Flush piotlb for SVM and Nested domain Yi Liu
  2026-01-06  7:56 ` Tian, Kevin
@ 2026-01-20  7:09 ` Baolu Lu
  1 sibling, 0 replies; 3+ messages in thread
From: Baolu Lu @ 2026-01-20  7:09 UTC (permalink / raw)
  To: Yi Liu, kevin.tian; +Cc: joro, iommu, jgg

On 12/23/25 14:58, Yi Liu wrote:
> Besides the paging domains that use FS, SVM and Nested domains need to
> use piotlb invalidation descriptor as well.
> 
> Fixes: b33125296b50 ("iommu/vt-d: Create unique domain ops for each stage")
> Signed-off-by: Yi Liu<yi.l.liu@intel.com>
> ---
> Change log:
> v2:
> - Use domain.type to filter nested and SVA type domain. This eliminates
>    the SVA domain ops reference issue when SVM is compiled out. (Kevin)
> - Add a intel_domain_use_piotlb() helper to cover the three cases which
>    need to flush piotlb. (Kevin)
> 
> v1:https://lore.kernel.org/linux-iommu/20251208091907.74719-1- 
> yi.l.liu@intel.com/
> ---
>   drivers/iommu/intel/cache.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)

Queued for iommu next.

Thanks,
baolu

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2026-01-20  7:09 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2025-12-23  6:58 [PATCH v2] iommu/vt-d: Flush piotlb for SVM and Nested domain Yi Liu
2026-01-06  7:56 ` Tian, Kevin
2026-01-20  7:09 ` Baolu Lu

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