Re: [PATCH 2/2] iommu: arm-smmu-v3: Report domain nesting info reuqired for stage1

[Vivek Kumar Gautam <vivek.gautam@arm.com>]

Hi Eric,


On 2/12/21 11:43 PM, Auger Eric wrote:
> Hi Vivek,
> 
> On 2/12/21 11:58 AM, Vivek Gautam wrote:
>> Update nested domain information required for stage1 page table.
> 
> s/reuqired/required in the commit title

My bad! Will correct it.

>>
>> Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
>> ---
>>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++--
>>   1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> index c11dd3940583..728018921fae 100644
>> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> @@ -2555,6 +2555,7 @@ static int arm_smmu_domain_nesting_info(struct arm_smmu_domain *smmu_domain,
>>   					void *data)
>>   {
>>   	struct iommu_nesting_info *info = (struct iommu_nesting_info *)data;
>> +	struct arm_smmu_device *smmu = smmu_domain->smmu;
>>   	unsigned int size;
>>   
>>   	if (!info || smmu_domain->stage != ARM_SMMU_DOMAIN_NESTED)
>> @@ -2571,9 +2572,20 @@ static int arm_smmu_domain_nesting_info(struct arm_smmu_domain *smmu_domain,
>>   		return 0;
>>   	}
>>   
>> -	/* report an empty iommu_nesting_info for now */
>> -	memset(info, 0x0, size);
>> +	/* Update the nesting info as required for stage1 page tables */
>> +	info->addr_width = smmu->ias;
>> +	info->format = IOMMU_PASID_FORMAT_ARM_SMMU_V3;
>> +	info->features = IOMMU_NESTING_FEAT_BIND_PGTBL |
> I understood IOMMU_NESTING_FEAT_BIND_PGTBL advertises the requirement to
> bind tables per PASID, ie. passing iommu_gpasid_bind_data.
> In ARM case I guess you plan to use attach/detach_pasid_table API with
> iommu_pasid_table_config struct. So I understood we should add a new
> feature here.

Right, the idea is to let vfio know that we support pasid table binding, and
  I thought we could use the same flag. But clearly that's not the case.
  I will add a new feature.

>> +			 IOMMU_NESTING_FEAT_PAGE_RESP |
>> +			 IOMMU_NESTING_FEAT_CACHE_INVLD;
>> +	info->pasid_bits = smmu->ssid_bits;
>> +	info->vendor.smmuv3.asid_bits = smmu->asid_bits;
>> +	info->vendor.smmuv3.pgtbl_fmt = ARM_64_LPAE_S1;
>> +	memset(&info->padding, 0x0, 12);
>> +	memset(&info->vendor.smmuv3.padding, 0x0, 9);
>> +
>>   	info->argsz = size;
>> +
> spurious new line

Sure, will correct this.

>>   	return 0;
>>   }
>>   
>>
> 

Thanks
Vivek
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