From: Klara Modin <klarasmodin@gmail.com>
To: Vasant Hegde <vasant.hegde@amd.com>,
iommu@lists.linux.dev, joro@8bytes.org
Cc: suravee.suthikulpanit@amd.com, wei.huang2@amd.com,
jsnitsel@redhat.com, jgg@ziepe.ca,
Jason Gunthorpe <jgg@nvidia.com>
Subject: Re: [PATCH v8 07/15] iommu/amd: Setup GCR3 table in advance if domain is SVA capable
Date: Mon, 6 May 2024 09:47:50 +0200 [thread overview]
Message-ID: <2a0d574d-6a3b-4344-9571-840eee569ae1@gmail.com> (raw)
In-Reply-To: <3488f733-c920-4e2a-86f7-05dc1779685e@amd.com>
On 2024-05-06 09:31, Vasant Hegde wrote:
> Hi Klara,
>
> Thanks for the report.
>
> Looking into the attached dmesg :
>
> 2024-04-29T10:35:05+02:00 soda.int.kasm.eu kernel: AMD-Vi: Using global IVHD
> EFR:0x0, EFR2:0x0
>
> --> This means BIOS didn't setup the EFR flags in ACPI IVRS table (its BIOS issue).
>
> Commit 8e0179733172 (iommu/amd: Enable Guest Translation before registering
> devices) changed GT feature enablement in control register.
>
> Now it tries to enable CONTROL[GT] flag before reading IOMMU feature register
> (late_iommu_features_init()).
>
> In attach device path, it assumed GT is supported (based on IOMMU EFR register
> value) and enabled DTE[GV]. Hence we hit ILLEGAL_DEV_TABLE_ENTRY error.
>
>
> Can you please try below fix?
>
>
> -Vasant
>
> ---
>
>
> diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
> index fd3e76e43699..b292181995b7 100644
> --- a/drivers/iommu/amd/init.c
> +++ b/drivers/iommu/amd/init.c
> @@ -2046,6 +2046,8 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
> amd_iommu_max_glx_val = glxval;
> else
> amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
> +
> + iommu_enable_gt(iommu);
> }
>
> if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu))
> @@ -2732,7 +2734,6 @@ static void early_enable_iommu(struct amd_iommu *iommu)
> iommu_enable_command_buffer(iommu);
> iommu_enable_event_buffer(iommu);
> iommu_set_exclusion_range(iommu);
> - iommu_enable_gt(iommu);
> iommu_enable_ga(iommu);
> iommu_enable_xt(iommu);
> iommu_enable_irtcachedis(iommu);
> @@ -2789,7 +2790,6 @@ static void early_enable_iommus(void)
> iommu_disable_irtcachedis(iommu);
> iommu_enable_command_buffer(iommu);
> iommu_enable_event_buffer(iommu);
> - iommu_enable_gt(iommu);
> iommu_enable_ga(iommu);
> iommu_enable_xt(iommu);
> iommu_enable_irtcachedis(iommu);
This fixes the issue for me.
Thanks,
Tested-by: Klara Modin <klarasmodin@gmail.com>
next prev parent reply other threads:[~2024-05-06 7:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 10:33 [PATCH v8 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 01/15] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 02/15] iommu/amd: Introduce per device DTE update function Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 03/15] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 04/15] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 05/15] iommu/amd: Fix PPR interrupt processing logic Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 06/15] iommu/amd: Introduce iommu_dev_data.max_pasids Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 07/15] iommu/amd: Setup GCR3 table in advance if domain is SVA capable Vasant Hegde
2024-05-02 13:16 ` Klara Modin
2024-05-03 10:26 ` Joerg Roedel
2024-05-06 6:42 ` Vasant Hegde
2024-05-06 7:31 ` Vasant Hegde
2024-05-06 7:47 ` Klara Modin [this message]
2024-05-06 8:15 ` Joerg Roedel
2024-05-06 8:25 ` Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 08/15] iommu/amd: Enable PCI features based on attached domain capability Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 09/15] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 10/15] iommu/amd: Add support for page response Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 11/15] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 12/15] iommu/amd: Add support for enable/disable IOPF Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 13/15] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 14/15] iommu: Add ops->domain_alloc_sva() Vasant Hegde
2024-04-18 10:34 ` [PATCH v8 15/15] iommu/amd: Add SVA domain support Vasant Hegde
2024-04-26 10:57 ` [PATCH v8 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF Joerg Roedel
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