[PATCH] iommu/vt-d: Present Access bit for IOVA in FL non-leaf paging entries

[PATCH] iommu/vt-d: Present Access bit for IOVA in FL non-leaf paging entries

[Tina Zhang]

The A/D bits are presented for IOVA over first level(FL) usage for both
kernel DMA (i.e, domain typs is IOMMU_DOMAIN_DMA) and user space DMA
usage (i.e., domain type is IOMMU_DOMAIN_UNMANAGED).

Preseting A bit in FL requires to present the bit in very related paging
entries, including the non-leaf ones. Otherwise, DMA fault may come out.
For example, in a case of ECAP_REG.SMPWC==0, the DMA fault would be
"SM: A/D bit update needed in first-level entry when set up in no
snoop".

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
---
 drivers/iommu/intel/iommu.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 48cdcd0a5cf3..996a8b5ee5ee 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -959,11 +959,9 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
 
 			domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
 			pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
-			if (domain_use_first_level(domain)) {
-				pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
-				if (iommu_is_dma_domain(&domain->domain))
-					pteval |= DMA_FL_PTE_ACCESS;
-			}
+			if (domain_use_first_level(domain))
+				pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;
+
 			if (cmpxchg64(&pte->val, 0ULL, pteval))
 				/* Someone else set it while we were thinking; use theirs. */
 				free_pgtable_page(tmp_page);
-- 
2.25.1

Re: [PATCH] iommu/vt-d: Present Access bit for IOVA in FL non-leaf paging entries

[Baolu Lu]

On 11/13/22 9:03 AM, Tina Zhang wrote:
> The A/D bits are presented for IOVA over first level(FL) usage for both
> kernel DMA (i.e, domain typs is IOMMU_DOMAIN_DMA) and user space DMA
> usage (i.e., domain type is IOMMU_DOMAIN_UNMANAGED).
> 
> Preseting A bit in FL requires to present the bit in very related paging
> entries, including the non-leaf ones. Otherwise, DMA fault may come out.
> For example, in a case of ECAP_REG.SMPWC==0, the DMA fault would be
> "SM: A/D bit update needed in first-level entry when set up in no
> snoop".
> 
> Signed-off-by: Tina Zhang <tina.zhang@intel.com>

Thanks for this patch.

Fixes: 289b3b005cb9 ("iommu/vt-d: Preset A/D bits for user space DMA usage")

Best regards,
baolu

> ---
>   drivers/iommu/intel/iommu.c | 8 +++-----
>   1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 48cdcd0a5cf3..996a8b5ee5ee 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -959,11 +959,9 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
>   
>   			domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
>   			pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
> -			if (domain_use_first_level(domain)) {
> -				pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
> -				if (iommu_is_dma_domain(&domain->domain))
> -					pteval |= DMA_FL_PTE_ACCESS;
> -			}
> +			if (domain_use_first_level(domain))
> +				pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;
> +
>   			if (cmpxchg64(&pte->val, 0ULL, pteval))
>   				/* Someone else set it while we were thinking; use theirs. */
>   				free_pgtable_page(tmp_page);

Re: [PATCH] iommu/vt-d: Present Access bit for IOVA in FL non-leaf paging entries

[Baolu Lu]

On 11/13/22 9:03 AM, Tina Zhang wrote:
> The A/D bits are presented for IOVA over first level(FL) usage for both
> kernel DMA (i.e, domain typs is IOMMU_DOMAIN_DMA) and user space DMA
> usage (i.e., domain type is IOMMU_DOMAIN_UNMANAGED).
> 
> Preseting A bit in FL requires to present the bit in very related paging
> entries, including the non-leaf ones. Otherwise, DMA fault may come out.
> For example, in a case of ECAP_REG.SMPWC==0, the DMA fault would be
> "SM: A/D bit update needed in first-level entry when set up in no
> snoop".
> 
> Signed-off-by: Tina Zhang<tina.zhang@intel.com>

Patch queued for v6.1. Thank you!

https://lore.kernel.org/linux-iommu/20221116051544.26540-1-baolu.lu@linux.intel.com/

Best regards,
baolu