From: Vasant Hegde <vasant.hegde@amd.com>
To: Sairaj Kodilkar <sarunkod@amd.com>,
joro@8bytes.org, iommu@lists.linux.dev
Cc: suravee.suthikulpanit@amd.com, will@kernel.org, robin.murphy@arm.com
Subject: Re: [PATCH 0/4] iommu/amd: Enable support for up to 2K interrupts per
Date: Thu, 13 Mar 2025 11:11:51 +0530 [thread overview]
Message-ID: <432bf54b-d0f0-4640-9afa-6df363bbe9d8@amd.com> (raw)
In-Reply-To: <20250307095822.2274-1-sarunkod@amd.com>
On 3/7/2025 3:28 PM, Sairaj Kodilkar wrote:
> Newer versions of the AMD platform can support up to 2K interrupts per
> function. This support can be enabled via field NumIntRemapMode in IOMMU
> control register (MMIO offset 0x0018).
>
> This series adds support to enable 2K interrupts per function on top of
> v6.14-rc5.
I have reviewed/tested this series. It looks good to me.
For entire series :
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
-Vasant
next prev parent reply other threads:[~2025-03-13 5:42 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-07 9:58 [PATCH 0/4] iommu/amd: Enable support for up to 2K interrupts per Sairaj Kodilkar
2025-03-07 9:58 ` [PATCH 1/4] iommu/amd: Introduce generic function to set multibit feature value Sairaj Kodilkar
2025-03-07 9:58 ` [PATCH 2/4] iommu/amd: Replace slab cache allocator with page allocator Sairaj Kodilkar
2025-03-07 9:58 ` [PATCH 3/4] iommu/amd: Rename DTE_INTTABLEN* and MAX_IRQS_PER_TABLE macro Sairaj Kodilkar
2025-03-07 9:58 ` [PATCH 4/4] iommu/amd: Enable support for up to 2K interrupts per function Sairaj Kodilkar
2025-03-13 5:41 ` Vasant Hegde [this message]
2025-03-13 11:15 ` [PATCH 0/4] iommu/amd: Enable support for up to 2K interrupts per Joerg Roedel
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