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From: Jason Gunthorpe <jgg@ziepe.ca>
To: Vasant Hegde <vasant.hegde@amd.com>, Baolu Lu <baolu.lu@linux.intel.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org,
	suravee.suthikulpanit@amd.com, wei.huang2@amd.com,
	jsnitsel@redhat.com
Subject: Re: [PATCH v2 10/11] iommu/amd: Add IO page fault notifier handler
Date: Tue, 12 Sep 2023 15:46:53 -0300	[thread overview]
Message-ID: <ZQCyHS9VFXZyAK4P@ziepe.ca> (raw)
In-Reply-To: <20230911121046.1025732-11-vasant.hegde@amd.com>

On Mon, Sep 11, 2023 at 12:10:45PM +0000, Vasant Hegde wrote:

> @@ -285,7 +286,7 @@ static struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid)
>  {
>  	struct iommu_dev_data *dev_data;
>  
> -	dev_data = search_dev_data(iommu, devid);
> +	dev_data = amd_iommu_search_dev_data(iommu, devid);

> +static bool ppr_is_valid(struct amd_iommu *iommu, u64 *raw)
> +{
> +	struct device *dev = iommu->iommu.dev;
> +	u16 devid = PPR_DEVID(raw[0]);
> +
> +	if (!(PPR_FLAGS(raw[0]) & PPR_FLAG_GN)) {
> +		dev_warn(dev, "PPR logged [Request ignored due to GN=0 (device=%04x:%02x:%02x.%x "
> +			 "pasid=0x%05llx address=0x%llx flags=0x%04llx tag=0x%03llx]\n",
> +			 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
> +			 PPR_PASID(raw[0]), raw[1], PPR_FLAGS(raw[0]), PPR_TAG(raw[0]));
> +		return false;
> +	}
> +
> +	if (PPR_FLAGS(raw[0]) & PPR_FLAG_RVSD) {
> +		dev_warn(dev, "PPR logged [Invalid request format (device=%04x:%02x:%02x.%x "
> +			 "pasid=0x%05llx address=0x%llx flags=0x%04llx tag=0x%03llx]\n",
> +			 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
> +			 PPR_PASID(raw[0]), raw[1], PPR_FLAGS(raw[0]), PPR_TAG(raw[0]));
> +		return false;
> +	}

Please be careful that no guest can trigger these warnings..

> +
> +	return true;
> +}
> +
> +static void iommu_call_iopf_notifier(struct amd_iommu *iommu, u64 *raw)
> +{
> +	struct iopf_fault event;
> +	struct pci_dev *pdev;
> +	int ret = -EINVAL;
> +	u16 devid = PPR_DEVID(raw[0]);
> +
> +	if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
> +		pr_err_ratelimited("Unknown PPR request received\n");
> +		return;
> +	}
> +
> +	if (!ppr_is_valid(iommu, raw))
> +		goto out;
> +
> +	pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
> +					   devid & 0xff);
> +	if (!pdev)
> +		goto out;

Lu, here is another case where the core PRI code could make use of a
core helper for a getting from the RID to the iommu world.

> +
> +	memset(&event, 0, sizeof(struct iopf_fault));
> +
> +	event.fault.type = IOMMU_FAULT_PAGE_REQ;
> +	event.fault.prm.perm = ppr_flag_to_fault_perm(PPR_FLAGS(raw[0]));
> +	event.fault.prm.addr = (u64)(raw[1] & PAGE_MASK);
> +	event.fault.prm.pasid = PPR_PASID(raw[0]);
> +	event.fault.prm.grpid = PPR_TAG(raw[0]) & 0x1FF;
> +
> +	/*
> +	 * PASID zero is used for requests from the I/O device without
> +	 * a PASID
> +	 */
> +	if (event.fault.prm.pasid == 0 ||
> +	    event.fault.prm.pasid >= pdev->dev.iommu->max_pasids) {
> +		pr_info_ratelimited("Invalid PASID : 0x%x, device : 0x%x\n",
> +				    event.fault.prm.pasid, pdev->dev.id);
> +		goto out;
> +	}
> +
> +
> +	event.fault.prm.flags |= IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID;
> +	event.fault.prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;
> +	if (PPR_TAG(raw[0]) & 0x200)
> +		event.fault.prm.flags |= IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE;
> +
> +	/* Submit event */
> +	ret = iommu_report_device_fault(&pdev->dev, &event);
> +
> +out:
> +	if (ret) {
> +		/* Nobody cared, abort */
> +		struct iommu_page_response resp = {
> +			.pasid = PPR_PASID(raw[0]),
> +			.grpid = PPR_TAG(raw[0]) & 0x1FF,
> +			.code = IOMMU_PAGE_RESP_FAILURE,
> +		};
> +		amd_iommu_page_response(&pdev->dev, &event, &resp);

Just to call amd_iommu_complete_ppr(), this already has the pci_dev,
we don't need amd_iommu_page_response() to get it.

Jason

  reply	other threads:[~2023-09-12 18:46 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-11 12:10 [PATCH v2 00/11] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 01/11] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_sva_supported() Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 02/11] iommu/amd: Do not override PASID entry in GCR3 table Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 03/11] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 04/11] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2023-09-12 16:47   ` Jason Gunthorpe
2023-09-15  8:50     ` Vasant Hegde
2023-09-18 12:53       ` Jason Gunthorpe
2023-10-13 15:52         ` Vasant Hegde
2023-10-13 15:58           ` Jason Gunthorpe
2023-09-11 12:10 ` [PATCH v2 05/11] iommu/amd: Add support to enable/disable PASID feature Vasant Hegde
2023-09-12 16:57   ` Jason Gunthorpe
2023-09-15  8:57     ` Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 06/11] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 07/11] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2023-09-12 16:59   ` Jason Gunthorpe
2023-09-15 13:48     ` Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 08/11] iommu/amd: Add support for page response Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 09/11] iommu/amd: Add support for add/remove device for IOPF Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 10/11] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2023-09-12 18:46   ` Jason Gunthorpe [this message]
2023-09-13  4:19     ` Baolu Lu
2023-09-15  8:15     ` Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 11/11] iommu/amd: Introduce logic to enable/disable IOPF Vasant Hegde
2023-09-12 16:32   ` Jason Gunthorpe
2023-09-15  8:26     ` Vasant Hegde
2023-09-18 12:45       ` Jason Gunthorpe
2023-10-10 14:53         ` Vasant Hegde
2023-10-10 15:04           ` Jason Gunthorpe
2023-09-12 18:48 ` [PATCH v2 00/11] iommu/amd: SVA Support (Part 4) - SVA and IOPF Jason Gunthorpe

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