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From: Naveen N Rao <naveen@kernel.org>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: Johannes Stezenbach <js@sig21.net>,
	iommu@lists.linux.dev,  Joerg Roedel <joro@8bytes.org>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
	 Mario Limonciello <superm1@kernel.org>
Subject: Re: AMD IOMMU issue with hibernate on Asrock X600
Date: Mon, 23 Feb 2026 11:47:09 +0530	[thread overview]
Message-ID: <aZvqJVoOpbdkZ5EY@blrnaveerao1> (raw)
In-Reply-To: <186731e2-a8f4-4402-9117-fc1dc737cfe9@amd.com>

On Sat, Feb 21, 2026 at 06:21:52PM +0530, Vasant Hegde wrote:
> Hi Johannes,
> 
> On 2/3/2026 5:10 PM, Johannes Stezenbach wrote:
> > On Tue, Feb 03, 2026 at 11:08:49AM +0530, Vasant Hegde wrote:
> >> On 1/28/2026 3:01 PM, Johannes Stezenbach wrote:
> >>>
> >>>> [0.000] [  343.790320][ T4340] WARNING: drivers/iommu/amd/init.c:952 at amd_iommu_enable_interrupts+0x4c8/0x550, CPU#0: pm-hibernate/4340
> >>>
> >>> - is it Linux or firmware bug?
> >>> - if Linux bug: please let me know what to do to help debug it
> >>> - if firmware bug: what additional tests to run; how to add a quirk
> >>>
> >>> What's the downside of amd_iommu_intr=legacy? Does it only
> >>> affect kvm guests? What's the relationship with x2APIC?
> >>
> >> If you pass `legacy`, then it only affects kvm. It will not accelerate
> >> interrupts to guest.
> >>
> >> interrupt acceleration has two modes:
> >>  AVIC works with xAPIC
> >>  X2AVIC works with X2APIC.
> >>
> >> Generally BIOS will automatically enables appropriate acceleration mode.
> > 
> > It is strange because dmesg says:
> > 
> > [    2.647593] [    T1] kvm_amd: AVIC enabled
> > [    2.647598] [    T1] kvm_amd: x2AVIC enabled (max 512 vCPUs)
> > 
> > but no message about x2APIC. If I enable x2APIC in BIOS (default
> > setting is "auto", other settings are "enable" or "disable") then
> > there is a message about x2APIC. So it seems BIOS default is
> > to have x2APIC disabled.

That is indeed weird - not really sure why x2APIC isn't enabled by 
default on that platform, or why amdgpu interrupts don't work with it.

> 
> Hmmm. This may be OK as AVIC/x2AVIC is used for guest interrupt delivery.
> 
> @Naveen, Can you look confirm is this config is fine?

With respect to x2AVIC, it will be enabled by the kernel as long as the 
platform says it supports it. It will obviously only kick in for guests 
running in x2APIC mode.


- Naveen


  reply	other threads:[~2026-02-23  6:19 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-26 14:54 AMD IOMMU issue with hibernate on Asrock X600 Johannes Stezenbach
2026-01-26 15:02 ` Asrock X600 port80 UART Johannes Stezenbach
2026-01-28  9:31 ` AMD IOMMU issue with hibernate on Asrock X600 Johannes Stezenbach
2026-02-03  5:38   ` Vasant Hegde
2026-02-03 11:40     ` Johannes Stezenbach
2026-02-04 15:16       ` Johannes Stezenbach
2026-02-05 14:05         ` Johannes Stezenbach
2026-02-21 14:31           ` Vasant Hegde
2026-02-21 20:28             ` Johannes Stezenbach
2026-02-23  8:49               ` Vasant Hegde
2026-02-23  9:09                 ` Johannes Stezenbach
2026-02-24  8:56                   ` Vasant Hegde
2026-02-24  9:11                     ` Johannes Stezenbach
2026-03-05 16:50                       ` Vasant Hegde
2026-02-21 13:14         ` Vasant Hegde
2026-02-21 12:51       ` Vasant Hegde
2026-02-23  6:17         ` Naveen N Rao [this message]
2026-02-03  5:28 ` Vasant Hegde
2026-02-03 11:49   ` Johannes Stezenbach

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