Re: AMD IOMMU issue with hibernate on Asrock X600

[Vasant Hegde <vasant.hegde@amd.com>]

Hi Johannes,


On 2/22/2026 1:58 AM, Johannes Stezenbach wrote:
> Hi Vasant,
> 
> On Sat, Feb 21, 2026 at 08:01:16PM +0530, Vasant Hegde wrote:
>> We have managed to reproduce the issue internally.
>>
>>
>> On 2/5/2026 7:35 PM, Johannes Stezenbach wrote:
>>> On Wed, Feb 04, 2026 at 04:16:51PM +0100, Johannes Stezenbach wrote:
>>>>
>>>> Side note: I wanted to check AMD documents at https://docs.amd.com/
>>>> but the "Create Account" button doesn't work. :-(
>>>> (And why do they require an account anyway, Intel and ARM don't...)
>>>
>>> Eventually I could download the "AMD I/O Virtualization Technology
>>> (IOMMU) Specification" document (link on https://uefi.org/acpi
>>> is stale, BTW).
>>
>>
>> Latest public spec -> https://docs.amd.com/v/u/en-US/48882_3.10_PUB
> 
> Yeah, found it already. I guess I used the wrong search terms,
> trying to find docs for the 8700G. Later I also found the 
> "AMD64 Architecture Programmer’s Manual Volume 2: System Programming"
> which has info on the APIC/xAPIC/x2APIC.
> 
>> If you have cycles, Can you try below patch (untested patch we will test it
>> internally next week)?
> 
> I tried it with 6.19.3, doesn't seem to work reliably, but the
> results are mixed, sometimes seems to work, sometimes doesn't.
> (Trying a mix of suspend and hibernate, and hibernate mutiple times.)


hmmm. Is there any pattern (like hibernate -> suspend failure) ?
Also do we have any other interesting message in dmesg?

I went through complete init code today. I don't see any other suspicious thing.
(disable -> enable sequence is proper).

-Vasant


> 
> I met the familiar
> 
> [  301.963784][ T5153] i >= MMIO_STATUS_TIMEOUT
> [  301.963786][ T5153] WARNING: drivers/iommu/amd/init.c:952 at amd_iommu_enable_interrupts+0x4c8/0x550, CPU#0: pm-hiber
> nate/5153
> ...
> [  302.304252][ T5153] Call Trace:                                                                                      [  302.312118][ T5153]  <TASK>
> [  302.319113][ T5153]  amd_iommu_reenable+0x10/0x20
> [  302.330910][ T5153]  lapic_resume+0x176/0x260
> 
> on hibernation entry (doesn't show up in dmesg, needs serial
> console) and also on hibernation resume after image loading
> (this shows up in dmesg).
> 
> 
> Thanks,
> Johannes
> 
> 
>> <--
>> commit fd6196203c8637951e56bf144015c020f57d5a34
>> Author: Vasant Hegde <vasant.hegde@amd.com>
>> Date:   Sat Feb 21 19:48:59 2026 +0530
>>
>>     iommu/amd: Skip IOMMU re-initialization if already enabled during resume
>>
>>     Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
>>
>> diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
>> index 384c90b4f90a..eb5bff024f95 100644
>> --- a/drivers/iommu/amd/init.c
>> +++ b/drivers/iommu/amd/init.c
>> @@ -3058,15 +3058,23 @@ static void disable_iommus(void)
>>  static void amd_iommu_resume(void *data)
>>  {
>>  	struct amd_iommu *iommu;
>> +	u64 ctrl;
>> +	bool enable_intr = false;
>>
>> -	for_each_iommu(iommu)
>> +	for_each_iommu(iommu) {
>> +		ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
>> +		if (ctrl & BIT_ULL(CONTROL_IOMMU_EN))
>> +			continue;
>> +
>> +		enable_intr = true;
>>  		iommu_apply_resume_quirks(iommu);
>>
>> -	/* re-load the hardware */
>> -	for_each_iommu(iommu)
>> +		/* re-load the hardware */
>>  		early_enable_iommu(iommu);
>> +	}
>>
>> -	amd_iommu_enable_interrupts();
>> +	if (enable_intr)
>> +		amd_iommu_enable_interrupts();
>>  }
>>
>>  static int amd_iommu_suspend(void *data)
>>
>>