From: Baolu Lu <baolu.lu@linux.intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Kevin Tian <kevin.tian@intel.com>, Jann Horn <jannh@google.com>,
Vasant Hegde <vasant.hegde@amd.com>,
Dave Hansen <dave.hansen@intel.com>,
Alistair Popple <apopple@nvidia.com>,
Uladzislau Rezki <urezki@gmail.com>,
Jean-Philippe Brucker <jean-philippe@linaro.org>,
Andy Lutomirski <luto@kernel.org>,
"Tested-by : Yi Lai" <yi1.lai@intel.com>,
iommu@lists.linux.dev, security@kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v2 1/1] iommu/sva: Invalidate KVA range on kernel TLB flush
Date: Thu, 17 Jul 2025 09:43:19 +0800 [thread overview]
Message-ID: <df5353e2-1d54-476b-90ab-e673686dcc41@linux.intel.com> (raw)
In-Reply-To: <20250716120817.GY2067380@nvidia.com>
On 7/16/25 20:08, Jason Gunthorpe wrote:
> On Wed, Jul 16, 2025 at 02:34:04PM +0800, Baolu Lu wrote:
>>>> @@ -654,6 +656,9 @@ struct iommu_ops {
>>>>
>>>> int (*def_domain_type)(struct device *dev);
>>>>
>>>> + void (*paging_cache_invalidate)(struct iommu_device *dev,
>>>> + unsigned long start, unsigned long end);
>>>
>>> How would you even implement this in a driver?
>>>
>>> You either flush the whole iommu, in which case who needs a rage, or
>>> the driver has to iterate over the PASID list, in which case it
>>> doesn't really improve the situation.
>>
>> The Intel iommu driver supports flushing all SVA PASIDs with a single
>> request in the invalidation queue.
>
> How? All PASID !=0 ? The HW has no notion about a SVA PASID vs no-SVA
> else. This is just flushing almost everything.
The intel iommu driver allocates a dedicated domain id for all sva
domains. It can flush all cache entries with that domain id tagged.
>
>>> If this is a concern I think the better answer is to do a defered free
>>> like the mm can sometimes do where we thread the page tables onto a
>>> linked list, flush the CPU cache and push it all into a work which
>>> will do the iommu flush before actually freeing the memory.
>>
>> Is it a workable solution to use schedule_work() to queue the KVA cache
>> invalidation as a work item in the system workqueue? By doing so, we
>> wouldn't need the spinlock to protect the list anymore.
>
> Maybe.
>
> MM is also more careful to pull the invalidation out some of the
> locks, I don't know what the KVA side is like..
How about something like the following? It's compiled but not tested.
struct kva_invalidation_work_data {
struct work_struct work;
unsigned long start;
unsigned long end;
bool free_on_completion;
};
static void invalidate_kva_func(struct work_struct *work)
{
struct kva_invalidation_work_data *data =
container_of(work, struct kva_invalidation_work_data, work);
struct iommu_mm_data *iommu_mm;
guard(mutex)(&iommu_sva_lock);
list_for_each_entry(iommu_mm, &iommu_sva_mms, mm_list_elm)
mmu_notifier_arch_invalidate_secondary_tlbs(iommu_mm->mm,
data->start, data->end);
if (data->free_on_completion)
kfree(data);
}
void iommu_sva_invalidate_kva_range(unsigned long start, unsigned long end)
{
struct kva_invalidation_work_data stack_data;
if (!static_branch_unlikely(&iommu_sva_present))
return;
/*
* Since iommu_sva_mms is an unbound list, iterating it in an atomic
* context could introduce significant latency issues.
*/
if (in_atomic()) {
struct kva_invalidation_work_data *data =
kzalloc(sizeof(*data), GFP_ATOMIC);
if (!data)
return;
data->start = start;
data->end = end;
INIT_WORK(&data->work, invalidate_kva_func);
data->free_on_completion = true;
schedule_work(&data->work);
return;
}
stack_data.start = start;
stack_data.end = end;
invalidate_kva_func(&stack_data.work);
}
Thanks,
baolu
next prev parent reply other threads:[~2025-07-17 1:45 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-09 6:28 [PATCH v2 1/1] iommu/sva: Invalidate KVA range on kernel TLB flush Lu Baolu
2025-07-09 15:29 ` Dave Hansen
2025-07-10 2:14 ` Baolu Lu
2025-07-10 2:55 ` Tian, Kevin
2025-07-10 12:53 ` Dave Hansen
2025-07-10 13:22 ` Jason Gunthorpe
2025-07-10 15:26 ` Dave Hansen
2025-07-11 2:46 ` Tian, Kevin
2025-07-11 2:54 ` Tian, Kevin
2025-07-11 8:17 ` Yu Zhang
2025-07-24 3:01 ` Baolu Lu
2025-07-28 17:36 ` Yu Zhang
2025-07-29 2:08 ` Baolu Lu
2025-07-24 3:06 ` Baolu Lu
2025-07-11 2:49 ` Tian, Kevin
2025-07-10 3:02 ` Tian, Kevin
2025-07-10 8:11 ` Yu Zhang
2025-07-10 8:15 ` Tian, Kevin
2025-07-10 9:37 ` Yu Zhang
2025-07-10 13:54 ` Peter Zijlstra
2025-07-10 15:53 ` Peter Zijlstra
2025-07-11 3:09 ` Baolu Lu
2025-07-11 8:27 ` Peter Zijlstra
2025-07-16 11:57 ` David Laight
2025-07-17 1:47 ` Baolu Lu
2025-07-11 3:00 ` Baolu Lu
2025-07-11 4:01 ` Tian, Kevin
2025-07-11 8:32 ` Peter Zijlstra
2025-07-11 11:58 ` Jason Gunthorpe
2025-07-15 5:55 ` Baolu Lu
2025-07-15 12:25 ` Jason Gunthorpe
2025-07-16 6:34 ` Baolu Lu
2025-07-16 12:08 ` Jason Gunthorpe
2025-07-17 1:43 ` Baolu Lu [this message]
2025-07-17 11:50 ` Vasant Hegde
2025-07-11 11:54 ` Jason Gunthorpe
2025-07-16 10:54 ` Yi Liu
2025-07-17 1:51 ` Baolu Lu
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