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From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: Robin Murphy <robin.murphy@arm.com>,
	"Tian, Kevin" <kevin.tian@intel.com>,
	"joro@8bytes.org" <joro@8bytes.org>,
	"will@kernel.org" <will@kernel.org>,
	"shuah@kernel.org" <shuah@kernel.org>,
	"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-kselftest@vger.kernel.org"
	<linux-kselftest@vger.kernel.org>
Subject: Re: [PATCH v2 2/3] iommu/dma: Support MSIs through nested domains
Date: Fri, 9 Aug 2024 12:18:42 -0700	[thread overview]
Message-ID: <ZrZrku/Av/y7ID0w@Asurada-Nvidia> (raw)
In-Reply-To: <20240809184136.GL8378@nvidia.com>

On Fri, Aug 09, 2024 at 03:41:36PM -0300, Jason Gunthorpe wrote:
> On Thu, Aug 08, 2024 at 01:38:44PM +0100, Robin Murphy wrote:
> > On 06/08/2024 9:25 am, Tian, Kevin wrote:
> > > > From: Nicolin Chen <nicolinc@nvidia.com>
> > > > Sent: Saturday, August 3, 2024 8:32 AM
> > > > 
> > > > From: Robin Murphy <robin.murphy@arm.com>
> > > > 
> > > > Currently, iommu-dma is the only place outside of IOMMUFD and drivers
> > > > which might need to be aware of the stage 2 domain encapsulated within
> > > > a nested domain. This would be in the legacy-VFIO-style case where we're
> > > 
> > > why is it a legacy-VFIO-style? We only support nested in IOMMUFD.
> > 
> > Because with proper nesting we ideally shouldn't need the host-managed MSI
> > mess at all, which all stems from the old VFIO paradigm of completely
> > abstracting interrupts from userspace. I'm still hoping IOMMUFD can grow its
> > own interface for efficient MSI passthrough, where the VMM can simply map
> > the physical MSI doorbell into whatever IPA (GPA) it wants it to appear at
> > in the S2 domain, then whatever the guest does with S1 it can program the
> > MSI address into the endpoint accordingly without us having to fiddle with
> > it.
> 
> +1
> 
> I don't have a staged plan to do this though. Getting the ITS page
> into the S2 at a user specified address should be simple enough to
> manage.
> 
> The bigger issue is that we still have the hypervisor GIC driver
> controlling things and it will need to know to use the guest provided
> MSI address captured during the MSI trap, not its own address. I don't
> have an idea how to connect those two parts yet.

You mean the gPA of the vITS v.s. PA of the ITS, right? I think
that's because only VMM knows the virtual IRQ number to insert?
We don't seem to have a choice for that unless we want to poke
a hole to the vGIC design..

With that, it feels a quite big improvement already by getting
rid of the entire shadow MSI mapping, including msi_cookie and
RMR..

Thanks
Nicolin

  reply	other threads:[~2024-08-09 19:18 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-03  0:32 [PATCH v2 0/3] iommufd: Add selftest coverage for reserved IOVAs Nicolin Chen
2024-08-03  0:32 ` [PATCH v2 1/3] iommufd: Reorder include files Nicolin Chen
2024-08-15 17:51   ` Jason Gunthorpe
2024-08-15 18:12     ` Nicolin Chen
2024-08-03  0:32 ` [PATCH v2 2/3] iommu/dma: Support MSIs through nested domains Nicolin Chen
2024-08-06  8:25   ` Tian, Kevin
2024-08-06 17:24     ` Nicolin Chen
2024-08-08 12:38     ` Robin Murphy
2024-08-08 22:59       ` Nicolin Chen
2024-08-09  8:00         ` Tian, Kevin
2024-08-09 17:43           ` Robin Murphy
2024-08-09 20:09             ` Nicolin Chen
2024-08-09 23:01           ` Jason Gunthorpe
2024-08-09  7:34       ` Tian, Kevin
2024-08-09 18:41       ` Jason Gunthorpe
2024-08-09 19:18         ` Nicolin Chen [this message]
2024-08-09 22:49           ` Jason Gunthorpe
2024-08-09 23:38             ` Nicolin Chen
2024-08-03  0:32 ` [PATCH v2 3/3] iommufd/selftest: Add coverage for reserved IOVAs Nicolin Chen
2024-08-09 15:52   ` kernel test robot

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