From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: Robin Murphy <robin.murphy@arm.com>,
"Tian, Kevin" <kevin.tian@intel.com>,
"joro@8bytes.org" <joro@8bytes.org>,
"will@kernel.org" <will@kernel.org>,
"shuah@kernel.org" <shuah@kernel.org>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-kselftest@vger.kernel.org"
<linux-kselftest@vger.kernel.org>
Subject: Re: [PATCH v2 2/3] iommu/dma: Support MSIs through nested domains
Date: Fri, 9 Aug 2024 16:38:21 -0700 [thread overview]
Message-ID: <Zraobe/Q9v3nsnmS@Asurada-Nvidia> (raw)
In-Reply-To: <20240809224910.GM8378@nvidia.com>
On Fri, Aug 09, 2024 at 07:49:10PM -0300, Jason Gunthorpe wrote:
> On Fri, Aug 09, 2024 at 12:18:42PM -0700, Nicolin Chen wrote:
>
> > > The bigger issue is that we still have the hypervisor GIC driver
> > > controlling things and it will need to know to use the guest provided
> > > MSI address captured during the MSI trap, not its own address. I don't
> > > have an idea how to connect those two parts yet.
> >
> > You mean the gPA of the vITS v.s. PA of the ITS, right? I think
> > that's because only VMM knows the virtual IRQ number to insert?
> > We don't seem to have a choice for that unless we want to poke
> > a hole to the vGIC design..
>
> I mean what you explained in your other email:
>
> > - MSI configuration in the host (via a VFIO_IRQ_SET_ACTION_TRIGGER
> > hypercall) should set gIOVA instead of fetching from msi_cookie.
> > That hypercall doesn't forward an address currently, since host
> > kernel pre-sets the msi_cookie. So, we need a way to forward the
> > gIOVA to kernel and pack it into the msi_msg structure. I haven't
> > read the VFIO PCI code thoroughly, yet wonder if we could just
> > let the guest program the gIOVA to the PCI register and fall it
> > through to the hardware, so host kernel handling that hypercall
> > can just read it back from the register?
>
> We still need to convay the MSI-X address from the register trap into
> the kernel and use the VM supplied address instead of calling
> iommu_dma_compose_msi_msg().
Yes.
> When you did your test you may have lucked out that the guest was
> putting the ITS at the same place the host kernel expected because
> they are both running the same software and making the same
> decision :)
Oh, the devil's in the details: I hard-coded every address in the
vITS's 2-stage mapping lol
> Maybe take a look at what pushing the address down through the
> VFIO_IRQ_SET_ACTION_TRIGGER would look like?
Yea, there's a data field and we can add a new flag to define the
format/type. Will take a closer look.
Thanks
Nicolin
next prev parent reply other threads:[~2024-08-09 23:38 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-03 0:32 [PATCH v2 0/3] iommufd: Add selftest coverage for reserved IOVAs Nicolin Chen
2024-08-03 0:32 ` [PATCH v2 1/3] iommufd: Reorder include files Nicolin Chen
2024-08-15 17:51 ` Jason Gunthorpe
2024-08-15 18:12 ` Nicolin Chen
2024-08-03 0:32 ` [PATCH v2 2/3] iommu/dma: Support MSIs through nested domains Nicolin Chen
2024-08-06 8:25 ` Tian, Kevin
2024-08-06 17:24 ` Nicolin Chen
2024-08-08 12:38 ` Robin Murphy
2024-08-08 22:59 ` Nicolin Chen
2024-08-09 8:00 ` Tian, Kevin
2024-08-09 17:43 ` Robin Murphy
2024-08-09 20:09 ` Nicolin Chen
2024-08-09 23:01 ` Jason Gunthorpe
2024-08-09 7:34 ` Tian, Kevin
2024-08-09 18:41 ` Jason Gunthorpe
2024-08-09 19:18 ` Nicolin Chen
2024-08-09 22:49 ` Jason Gunthorpe
2024-08-09 23:38 ` Nicolin Chen [this message]
2024-08-03 0:32 ` [PATCH v2 3/3] iommufd/selftest: Add coverage for reserved IOVAs Nicolin Chen
2024-08-09 15:52 ` kernel test robot
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