* [PATCH 0/2] m68knommu: better support for ColdFire external interrupts @ 2011-03-14 0:36 gerg 2011-03-14 0:36 ` [PATCH 1/2] m68knommu: external interrupt support to ColdFire intc-2 controller gerg 0 siblings, 1 reply; 3+ messages in thread From: gerg @ 2011-03-14 0:36 UTC (permalink / raw) To: linux-m68k, uclinux-dev Implement proper setup and support for the external interrupts on the newer families of ColdFire CPUs. Most of them offer up to 7 external (that is not on-chip) interrupts, and there is some extra effort required to init them, and ack them. ^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/2] m68knommu: external interrupt support to ColdFire intc-2 controller 2011-03-14 0:36 [PATCH 0/2] m68knommu: better support for ColdFire external interrupts gerg @ 2011-03-14 0:36 ` gerg 2011-03-14 0:36 ` [PATCH 2/2] m68knommu: external interrupt support to ColdFire intc-simr controller gerg 0 siblings, 1 reply; 3+ messages in thread From: gerg @ 2011-03-14 0:36 UTC (permalink / raw) To: linux-m68k, uclinux-dev; +Cc: Greg Ungerer From: Greg Ungerer <gerg@uclinux.org> The EDGE Port module of some ColdFire parts using the intc-2 interrupt controller provides support for 7 external interrupts. These interrupts go off-chip (that is they are not for internal peripherals). They need some special handling and have some extra setup registers. Add code to support them. Signed-off-by: Greg Ungerer <gerg@uclinux.org> --- arch/m68k/include/asm/m523xsim.h | 3 + arch/m68k/include/asm/m527xsim.h | 3 + arch/m68k/include/asm/m54xxsim.h | 10 ++++ arch/m68knommu/platform/coldfire/intc-2.c | 85 +++++++++++++++++++++++++++-- 4 files changed, 97 insertions(+), 4 deletions(-) diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 3852f07..8996df6 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -139,9 +139,12 @@ /* * EPort */ +#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) +#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) +#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) /* * Generic GPIO support diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index c23046e..74855a6 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -259,9 +259,12 @@ /* * EPort */ +#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) +#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) +#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) /* * GPIO pins setups to enable the UARTs. diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index daaae27..1ed8bfb 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -50,6 +50,16 @@ #define MCFGPIO_IRQ_VECBASE -1 /* + * EDGE Port support. + */ +#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ +#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ +#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ +#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ +#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ +#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ + +/* * Some PSC related definitions */ #define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c index 66d4e47..2cbfbf0 100644 --- a/arch/m68knommu/platform/coldfire/intc-2.c +++ b/arch/m68knommu/platform/coldfire/intc-2.c @@ -7,7 +7,10 @@ * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such * controllers, and the 547x and 548x families which have only one of them. * - * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> + * The external 7 fixed interrupts are part the the Edge Port unit of these + * ColdFire parts. They can be configured as level or edge triggered. + * + * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive @@ -30,6 +33,14 @@ #define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */ #define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */ +/* + * The EDGE Port interrupts are the fixed 7 external interrupts. + * They need some special treatment, for example they need to be acked. + */ +#define EINT0 64 /* Is not actually used, but spot reserved for it */ +#define EINT1 65 /* EDGE Port interrupt 1 */ +#define EINT7 71 /* EDGE Port interrupt 7 */ + #ifdef MCFICM_INTC1 #define NR_VECS 128 #else @@ -76,9 +87,17 @@ static void intc_irq_unmask(struct irq_data *d) __raw_writel(val & ~imrbit, imraddr); } -static int intc_irq_set_type(struct irq_data *d, unsigned int type) +/* + * Only the external (or EDGE Port) interrupts need to be acknowledged + * here, as part of the IRQ handler. They only really need to be ack'ed + * if they are in edge triggered mode, but there is no harm in doing it + * for all types. + */ +static void intc_irq_ack(struct irq_data *d) { - return 0; + unsigned int irq = d->irq; + + __raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR); } /* @@ -104,15 +123,70 @@ static unsigned int intc_irq_startup(struct irq_data *d) if (__raw_readb(icraddr) == 0) __raw_writeb(intc_intpri--, icraddr); + irq = d->irq; + if ((irq >= EINT1) && (irq <= EINT7)) { + u8 v; + + irq -= EINT0; + + /* Set EPORT line as input */ + v = __raw_readb(MCFEPORT_EPDDR); + __raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR); + + /* Set EPORT line as interrupt source */ + v = __raw_readb(MCFEPORT_EPIER); + __raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER); + } + intc_irq_unmask(d); return 0; } +static int intc_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int irq = d->irq; + u16 pa, tb; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + tb = 0x1; + break; + case IRQ_TYPE_EDGE_FALLING: + tb = 0x2; + break; + case IRQ_TYPE_EDGE_BOTH: + tb = 0x3; + break; + default: + /* Level triggered */ + tb = 0; + break; + } + + if (tb) + set_irq_handler(irq, handle_edge_irq); + + irq -= EINT0; + pa = __raw_readw(MCFEPORT_EPPAR); + pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2)); + __raw_writew(pa, MCFEPORT_EPPAR); + + return 0; +} + static struct irq_chip intc_irq_chip = { .name = "CF-INTC", .irq_startup = intc_irq_startup, .irq_mask = intc_irq_mask, .irq_unmask = intc_irq_unmask, +}; + +static struct irq_chip intc_irq_chip_edge_port = { + .name = "CF-INTC-EP", + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_ack = intc_irq_ack, .irq_set_type = intc_irq_set_type, }; @@ -129,7 +203,10 @@ void __init init_IRQ(void) #endif for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { - set_irq_chip(irq, &intc_irq_chip); + if ((irq >= EINT1) && (irq <=EINT7)) + set_irq_chip(irq, &intc_irq_chip_edge_port); + else + set_irq_chip(irq, &intc_irq_chip); set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); set_irq_handler(irq, handle_level_irq); } -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] m68knommu: external interrupt support to ColdFire intc-simr controller 2011-03-14 0:36 ` [PATCH 1/2] m68knommu: external interrupt support to ColdFire intc-2 controller gerg @ 2011-03-14 0:36 ` gerg 0 siblings, 0 replies; 3+ messages in thread From: gerg @ 2011-03-14 0:36 UTC (permalink / raw) To: linux-m68k, uclinux-dev; +Cc: Greg Ungerer From: Greg Ungerer <gerg@uclinux.org> The EDGE Port module of some ColdFire parts using the intc-simr interrupt controller provides support for 7 external interrupts. These interrupts go off-chip (that is they are not for internal peripherals). They need some special handling and have some extra setup registers. Add code to support them. Signed-off-by: Greg Ungerer <gerg@uclinux.org> --- arch/m68k/include/asm/m520xsim.h | 3 + arch/m68knommu/platform/coldfire/intc-simr.c | 114 +++++++++++++++++++++++++- 2 files changed, 113 insertions(+), 4 deletions(-) diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index ee89801..55d5a4c 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -63,9 +63,12 @@ /* * EPORT and GPIO registers. */ +#define MCFEPORT_EPPAR 0xFC088000 #define MCFEPORT_EPDDR 0xFC088002 +#define MCFEPORT_EPIER 0xFC088003 #define MCFEPORT_EPDR 0xFC088004 #define MCFEPORT_EPPDR 0xFC088005 +#define MCFEPORT_EPFR 0xFC088006 #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 #define MCFGPIO_PODR_BE 0xFC0A4001 diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c index 8876f43..e642b24 100644 --- a/arch/m68knommu/platform/coldfire/intc-simr.c +++ b/arch/m68knommu/platform/coldfire/intc-simr.c @@ -3,7 +3,7 @@ * * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts. * - * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> + * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive @@ -21,6 +21,44 @@ #include <asm/traps.h> /* + * The EDGE Port interrupts are the fixed 7 external interrupts. + * They need some special treatment, for example they need to be acked. + */ +#ifdef CONFIG_M520x +/* + * The 520x parts only support a limited range of these external + * interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67). + */ +#define EINT0 64 /* Is not actually used, but spot reserved for it */ +#define EINT1 65 /* EDGE Port interrupt 1 */ +#define EINT4 66 /* EDGE Port interrupt 4 */ +#define EINT7 67 /* EDGE Port interrupt 7 */ + +static unsigned int irqebitmap[] = { 0, 1, 4, 7 }; +static unsigned int inline irq2ebit(unsigned int irq) +{ + return irqebitmap[irq - EINT0]; +} + +#else + +/* + * Most of the ColdFire parts with the EDGE Port module just have + * a strait direct mapping of the 7 external interrupts. Although + * there is a bit reserved for 0, it is not used. + */ +#define EINT0 64 /* Is not actually used, but spot reserved for it */ +#define EINT1 65 /* EDGE Port interrupt 1 */ +#define EINT7 71 /* EDGE Port interrupt 7 */ + +static unsigned int inline irq2ebit(unsigned int irq) +{ + return irq - EINT0; +} + +#endif + +/* * There maybe one or two interrupt control units, each has 64 * interrupts. If there is no second unit then MCFINTC1_* defines * will be 0 (and code for them optimized away). @@ -46,21 +84,86 @@ static void intc_irq_unmask(struct irq_data *d) __raw_writeb(irq, MCFINTC0_CIMR); } -static int intc_irq_set_type(struct irq_data *d, unsigned int type) +static void intc_irq_ack(struct irq_data *d) { - unsigned int irq = d->irq - MCFINT_VECBASE; + unsigned int ebit = irq2ebit(d->irq); + __raw_writeb(0x1 << ebit, MCFEPORT_EPFR); +} + +static unsigned int intc_irq_startup(struct irq_data *d) +{ + unsigned int irq = d->irq; + + if ((irq >= EINT1) && (irq <= EINT7)) { + unsigned int ebit = irq2ebit(irq); + u8 v; + + /* Set EPORT line as input */ + v = __raw_readb(MCFEPORT_EPDDR); + __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR); + + /* Set EPORT line as interrupt source */ + v = __raw_readb(MCFEPORT_EPIER); + __raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER); + } + + irq -= MCFINT_VECBASE; if (MCFINTC1_ICR0 && (irq > 64)) __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); else __raw_writeb(5, MCFINTC0_ICR0 + irq); + + + intc_irq_unmask(d); + return 0; +} + +static int intc_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int ebit, irq = d->irq; + u16 pa, tb; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + tb = 0x1; + break; + case IRQ_TYPE_EDGE_FALLING: + tb = 0x2; + break; + case IRQ_TYPE_EDGE_BOTH: + tb = 0x3; + break; + default: + /* Level triggered */ + tb = 0; + break; + } + + if (tb) + set_irq_handler(irq, handle_edge_irq); + + ebit = irq2ebit(irq) * 2; + pa = __raw_readw(MCFEPORT_EPPAR); + pa = (pa & ~(0x3 << ebit)) | (tb << ebit); + __raw_writew(pa, MCFEPORT_EPPAR); + return 0; } static struct irq_chip intc_irq_chip = { .name = "CF-INTC", + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, +}; + +static struct irq_chip intc_irq_chip_edge_port = { + .name = "CF-INTC-EP", + .irq_startup = intc_irq_startup, .irq_mask = intc_irq_mask, .irq_unmask = intc_irq_unmask, + .irq_ack = intc_irq_ack, .irq_set_type = intc_irq_set_type, }; @@ -77,7 +180,10 @@ void __init init_IRQ(void) eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { - set_irq_chip(irq, &intc_irq_chip); + if ((irq >= EINT1) && (irq <= EINT7)) + set_irq_chip(irq, &intc_irq_chip_edge_port); + else + set_irq_chip(irq, &intc_irq_chip); set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); set_irq_handler(irq, handle_level_irq); } -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2011-03-14 0:37 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-03-14 0:36 [PATCH 0/2] m68knommu: better support for ColdFire external interrupts gerg 2011-03-14 0:36 ` [PATCH 1/2] m68knommu: external interrupt support to ColdFire intc-2 controller gerg 2011-03-14 0:36 ` [PATCH 2/2] m68knommu: external interrupt support to ColdFire intc-simr controller gerg
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