* Re: [patch V3] lib: GCD: add binary GCD algorithm
[not found] <1461843824-19853-1-git-send-email-zengzhaoxiu@163.com>
@ 2016-04-28 12:18 ` kbuild test robot
2016-04-28 16:48 ` George Spelvin
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: kbuild test robot @ 2016-04-28 12:18 UTC (permalink / raw)
To: zengzhaoxiu
Cc: kbuild-all, akpm, linux, peterz, Zhaoxiu Zeng, Richard Henderson,
Ivan Kokshaysky, Matt Turner, Russell King, Yoshinori Sato,
Geert Uytterhoeven, James Hogan, Michal Simek, Ralf Baechle,
Ley Foon Tan, Jonas Bonn, James E.J. Bottomley, Helge Deller,
Chen Liqin, Lennox Wu, Rich Felker, David S. Miller, linux-kernel,
linux-alpha, linux-arm-kernel, uclinux-h8-devel
[-- Attachment #1: Type: text/plain, Size: 14162 bytes --]
Hi,
[auto build test ERROR on v4.6-rc5]
[cannot apply to next-20160428]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/zengzhaoxiu-163-com/lib-GCD-add-binary-GCD-algorithm/20160428-195527
config: mips-allyesconfig (attached as .config)
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=mips
All error/warnings (new ones prefixed by >>):
In file included from arch/mips/include/asm/bitops.h:21:0,
from include/linux/bitops.h:36,
from include/linux/kernel.h:10,
from include/asm-generic/bug.h:13,
from arch/mips/include/asm/bug.h:41,
from include/linux/bug.h:4,
from include/linux/page-flags.h:9,
from kernel/bounds.c:9:
>> arch/mips/include/asm/cpu-features.h:205:28: warning: "cpu_data" is not defined [-Wundef]
# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
^
>> arch/mips/include/asm/cpu-features.h:241:5: note: in expansion of macro 'cpu_has_mips32r6'
cpu_has_mips32r6 | cpu_has_mips64r1 | \
^
>> arch/mips/include/asm/cpu-features.h:289:25: note: in expansion of macro 'cpu_has_mips_r'
#define cpu_has_clo_clz cpu_has_mips_r
^
>> arch/mips/include/asm/cpu-features.h:291:6: note: in expansion of macro 'cpu_has_clo_clz'
#if !cpu_has_clo_clz
^
>> arch/mips/include/asm/cpu-features.h:205:36: error: token "[" is not valid in preprocessor expressions
# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
^
>> arch/mips/include/asm/cpu-features.h:241:5: note: in expansion of macro 'cpu_has_mips32r6'
cpu_has_mips32r6 | cpu_has_mips64r1 | \
^
>> arch/mips/include/asm/cpu-features.h:289:25: note: in expansion of macro 'cpu_has_mips_r'
#define cpu_has_clo_clz cpu_has_mips_r
^
>> arch/mips/include/asm/cpu-features.h:291:6: note: in expansion of macro 'cpu_has_clo_clz'
#if !cpu_has_clo_clz
^
make[2]: *** [kernel/bounds.s] Error 1
make[2]: Target '__build' not remade because of errors.
make[1]: *** [prepare0] Error 2
make[1]: Target 'prepare' not remade because of errors.
make: *** [sub-make] Error 2
vim +205 arch/mips/include/asm/cpu-features.h
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 199 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 200 #endif
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 201 #ifndef cpu_has_mips32r2
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 202 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 203 #endif
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 204 #ifndef cpu_has_mips32r6
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 @205 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 206 #endif
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 207 #ifndef cpu_has_mips64r1
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 208 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 209 #endif
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 210 #ifndef cpu_has_mips64r2
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 211 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 212 #endif
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 213 #ifndef cpu_has_mips64r6
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 214 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 215 #endif
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 216
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 217 /*
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 218 * Shortcuts ...
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 219 */
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 220 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 221 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 222 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 223
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 224 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 225 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 226 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 227 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 228
2d83fea78 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 229 #define cpu_has_mips_3_4_5_64_r2_r6 \
2d83fea78 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 230 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
2d83fea78 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 231 #define cpu_has_mips_4_5_64_r2_r6 \
2d83fea78 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 232 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \
2d83fea78 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 233 cpu_has_mips_r2 | cpu_has_mips_r6)
08a07904e arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 234
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 235 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 236 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 237 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 238 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 239 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
c46b302b9 arch/mips/include/asm/cpu-features.h Ralf Baechle 2008-10-28 240 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 @241 cpu_has_mips32r6 | cpu_has_mips64r1 | \
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 242 cpu_has_mips64r2 | cpu_has_mips64r6)
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 243
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 244 /* MIPSR2 and MIPSR6 have a lot of similarities */
34c56fc1c arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 245 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
0401572a9 include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 246
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 247 /*
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 248 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 249 *
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 250 * Returns non-zero value if the current processor implementation requires
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 251 * an IHB instruction to deal with an instruction hazard as per MIPS R2
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 252 * architecture specification, zero otherwise.
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 253 */
41f0e4d04 arch/mips/include/asm/cpu-features.h David Daney 2009-05-12 254 #ifndef cpu_has_mips_r2_exec_hazard
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 255 #define cpu_has_mips_r2_exec_hazard \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 256 ({ \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 257 int __res; \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 258 \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 259 switch (current_cpu_type()) { \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 260 case CPU_M14KC: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 261 case CPU_74K: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 262 case CPU_1074K: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 263 case CPU_PROAPTIV: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 264 case CPU_P5600: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 265 case CPU_M5150: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 266 case CPU_QEMU_GENERIC: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 267 case CPU_CAVIUM_OCTEON: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 268 case CPU_CAVIUM_OCTEON_PLUS: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 269 case CPU_CAVIUM_OCTEON2: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 270 case CPU_CAVIUM_OCTEON3: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 271 __res = 0; \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 272 break; \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 273 \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 274 default: \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 275 __res = 1; \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 276 } \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 277 \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 278 __res; \
9cdf30bd3 arch/mips/include/asm/cpu-features.h Ralf Baechle 2015-03-25 279 })
41f0e4d04 arch/mips/include/asm/cpu-features.h David Daney 2009-05-12 280 #endif
41f0e4d04 arch/mips/include/asm/cpu-features.h David Daney 2009-05-12 281
47740eb88 arch/mips/include/asm/cpu-features.h Ralf Baechle 2009-04-19 282 /*
47740eb88 arch/mips/include/asm/cpu-features.h Ralf Baechle 2009-04-19 283 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
becee6b8c arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2013-09-22 284 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
417a5eb02 arch/mips/include/asm/cpu-features.h Ralf Baechle 2010-08-05 285 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
47740eb88 arch/mips/include/asm/cpu-features.h Ralf Baechle 2009-04-19 286 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
47740eb88 arch/mips/include/asm/cpu-features.h Ralf Baechle 2009-04-19 287 */
47740eb88 arch/mips/include/asm/cpu-features.h Ralf Baechle 2009-04-19 288 #ifndef cpu_has_clo_clz
47740eb88 arch/mips/include/asm/cpu-features.h Ralf Baechle 2009-04-19 @289 #define cpu_has_clo_clz cpu_has_mips_r
47740eb88 arch/mips/include/asm/cpu-features.h Ralf Baechle 2009-04-19 290 #endif
35e1a24e8 arch/mips/include/asm/cpu-features.h Zhaoxiu Zeng 2016-04-28 @291 #if !cpu_has_clo_clz
35e1a24e8 arch/mips/include/asm/cpu-features.h Zhaoxiu Zeng 2016-04-28 292 #define CONFIG_CPU_NO_EFFICIENT_FFS 1
35e1a24e8 arch/mips/include/asm/cpu-features.h Zhaoxiu Zeng 2016-04-28 293 #endif
47740eb88 arch/mips/include/asm/cpu-features.h Ralf Baechle 2009-04-19 294
:::::: The code at line 205 was first introduced by commit
:::::: 34c56fc1c167facc375d927687df0a3891d164ac MIPS: asm: cpu: Add MIPSR6 ISA definitions
:::::: TO: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
:::::: CC: Markos Chandras <markos.chandras@imgtec.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 41439 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [patch V3] lib: GCD: add binary GCD algorithm
[not found] <1461843824-19853-1-git-send-email-zengzhaoxiu@163.com>
2016-04-28 12:18 ` [patch V3] lib: GCD: add binary GCD algorithm kbuild test robot
@ 2016-04-28 16:48 ` George Spelvin
2016-04-28 17:10 ` Josh Juran
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: George Spelvin @ 2016-04-28 16:48 UTC (permalink / raw)
To: akpm, linux, peterz, zengzhaoxiu
Cc: dalias, davem, deller, geert, ink, james.hogan, jejb, jonas,
lennox.wu, lftan, linux-alpha, linux-arm-kernel, linux-kernel,
linux-m68k, linux-metag, linux-mips, linux-parisc, linux-sh,
linux, linux, liqin.linux, mattst88, monstr, nios2-dev, ralf, rth,
sparclinux, uclinux-h8-devel, ysato, zhaoxiu.zeng
Another few comments:
1. Would ARCH_HAS_FAST_FFS involve fewer changes than CPU_NO_EFFICIENT_FFS?
Rather than updating all the Kconfig files, it could be #defined in
the arch/*/asm/bitops.h files where the __ffs macro is defined. E.g.
diff --git a/arch/alpha/include/asm/bitops.h b/arch/alpha/include/asm/bitops.h
index 4bdfbd44..c9c307a8 100644
--- a/arch/alpha/include/asm/bitops.h
+++ b/arch/alpha/include/asm/bitops.h
@@ -333,6 +333,7 @@ static inline unsigned long ffz(unsigned long word)
static inline unsigned long __ffs(unsigned long word)
{
#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
+#define ARCH_HAS_FAST_FFS 1
/* Whee. EV67 can calculate it directly. */
return __kernel_cttz(word);
#else
Looking at the available architectures (list below), it looks like we
have 9 with fast __ffs, 13 without, and 7 where it depends on the model.
Three of the architectures without could have one written.
In terms of code changes, ARCH_HAS_SLOW_FFS would be slightly smaller,
inserting it into the asm-generic version and the few arch-specific
versions (marked "NO" below) which have optimized but bit-at-a-time code.
__ffs on the available architectures:
Alpha: sometimes (CONFIG_ALPHA_EV6, CONFIG_ALPHA_EV67)
ARC: sometimes (!CONFIG_ISA_ARCOMPACT)
ARM: sometimes (V5+)
ARM64: NO, could be written using RBIT and CLZ
AVR: yes
Blackfin: NO, could be written using hweight()
C6x: yes
CRIS: NO
FR-V: yes
H8300: NO
Hexagon: yes
IA64: yes
M32R: NO
M68k: sometimes
MetaG: NO
Microblaze: NO
MIPS: sometimes
MN10300: yes
OpenRISC: NO
PA-RISC: NO? Interesting code, but I think it's a net loss.
PowerPC: yes
S390: sometimes (CONFIG_HAVE_MARCH_Z9_109_FEATURES)
Score: NO
SH: NO
SPARC: NO
Tile: NO, could be written using hweight()
Unicore32: yes
x86: yes
Xtensa: sometimes (XCHAL_HAVE_NSA)
2. The documentation could definitely be improved. If I may humbly
recommend something like the following. I think it's particularly
important to say in the summary line that this is replacing something
rather than adding (which sets off code bloat alarms).
+Subject: lib: GCD: Use binary GCD algorithm instead of Euclidean
+
+Even on x86 machines with reasonable division hardware, the binary
+algorithm runs about 25% faster (80% the execution time) than the
+division-based Euclidian algorithm.
+
+On platforms like Alpha and ARMv6 where division is a function call to
+emulation code, it's even more significant.
+
+There are two variants of the code here, depending on whether a
+fast __ffs (find least significant set bit) instruction is available.
+This allows the unpredictable branches in the bit-at-a-time shifting
+loop to be eliminated.
+
+If fast __ffs is not available, the "even/odd" GCD variant is used.
+This adds an additional test in the loop to choose between
+(a-b)/4 and (a+b)/4, dividing by 4 each iteration. If fast __ffs
+is available, this doesn't help.
3. The benchmarking could be made more realistic. Zhaoxiu Zeng's test
program uses full-width random inputs. However, if there is a large
difference in the size of the inputs, it takes the binary algorithm
many steps to do what division does in one.
(Aside: I'd use informal address, but I don't know which name to use.
Are those names in Western given-family order Zhaoxiu ZENG, or Eastern
family-given order ZHAOXIU Zeng?)
For example, if I benchmark
gcd(random64(), 1000000)
the binary code is barely faster on a Phenom, and if I drop that to
1000, it's actually 25% slower. On Ivy Bridge, the binary code is
still consistently faster in both cases.
On a Pentium 4, if anyone cares, the binary code is 2.4x faster
on full-width inputs (32 bits in this case!), 25% faster with a fixed
1,000,000 and about 7% slower with a fixed 1,000.
It still seems like a net win to me, especially as the large speedups
apply to the worst case (so you're saving large*large), while the
slowdowns apply to the best case (you're losing small*small).
But if someone wants to do suggest more realistic benchmark conditions,
it would be interesting.
This entire function isn't actually used in any performance-sensitive
places AFAICT, so it's not very important one way or another, but I
understand the urge.
One way I changed the benchmark program was to eliminate the sleep(1)
calls, bump the iteration count 100-fold, and do two passes over the
list of, discarding the first one.
Without that, the Euclidean algorithm, being the first to run, gets a
huge penalty due to the CPU throttling up in the middle of its run.
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [patch V3] lib: GCD: add binary GCD algorithm
[not found] <1461843824-19853-1-git-send-email-zengzhaoxiu@163.com>
2016-04-28 12:18 ` [patch V3] lib: GCD: add binary GCD algorithm kbuild test robot
2016-04-28 16:48 ` George Spelvin
@ 2016-04-28 17:10 ` Josh Juran
2016-04-28 17:22 ` James Bottomley
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Josh Juran @ 2016-04-28 17:10 UTC (permalink / raw)
To: zengzhaoxiu
Cc: akpm, linux, peterz, Zhaoxiu Zeng, Richard Henderson,
Ivan Kokshaysky, Matt Turner, Russell King, Yoshinori Sato,
Geert Uytterhoeven, James Hogan, Michal Simek, Ralf Baechle,
Ley Foon Tan, Jonas Bonn, James E.J. Bottomley, Helge Deller,
Chen Liqin, Lennox Wu, Rich Felker, David S. Miller, linux-kernel,
linux-alpha, linux-arm-kernel, uclinux-h8-devel
On Apr 28, 2016, at 7:43 AM, zengzhaoxiu@163.com wrote:
> + * This implements the binary GCD algorithm. (Often attributed to Stein,
> + * but as Knuth has noted, appears a first-century Chinese math text.)
Should this be "appears in a"?
Josh
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [patch V3] lib: GCD: add binary GCD algorithm
[not found] <1461843824-19853-1-git-send-email-zengzhaoxiu@163.com>
` (2 preceding siblings ...)
2016-04-28 17:10 ` Josh Juran
@ 2016-04-28 17:22 ` James Bottomley
[not found] ` <20160428164856.10120.qmail@ns.horizon.com>
2016-05-20 10:27 ` kbuild test robot
5 siblings, 0 replies; 11+ messages in thread
From: James Bottomley @ 2016-04-28 17:22 UTC (permalink / raw)
To: zengzhaoxiu, akpm, linux, peterz
Cc: Zhaoxiu Zeng, Richard Henderson, Ivan Kokshaysky, Matt Turner,
Russell King, Yoshinori Sato, Geert Uytterhoeven, James Hogan,
Michal Simek, Ralf Baechle, Ley Foon Tan, Jonas Bonn,
James E.J. Bottomley, Helge Deller, Chen Liqin, Lennox Wu,
Rich Felker, David S. Miller, linux-kernel, linux-alpha,
linux-arm-kernel, uclinux-h8-devel, linux-m68k, linux-metag
On Thu, 2016-04-28 at 19:43 +0800, zengzhaoxiu@163.com wrote:
> From: Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com>
>
> Because some architectures (alpha, armv6, etc.) don't provide
> hardware division, the mod operation is slow! Binary GCD algorithm
> uses simple arithmetic operations, it replaces division with
> arithmetic shifts, comparisons, and subtractions.
>
> I have compiled successfully with x86_64_defconfig and
> i386_defconfig.
What's the reason for wanting to optimize this and thus have to
maintain (and test) two separate code paths, which is a significant
expense? As far as I can see, gcd() is mosly used in finding optimal
clocks for operations, which is usually done at start of day and not
time critical.
James
^ permalink raw reply [flat|nested] 11+ messages in thread[parent not found: <20160428164856.10120.qmail@ns.horizon.com>]
* Re: [patch V3] lib: GCD: add binary GCD algorithm
[not found] ` <20160428164856.10120.qmail@ns.horizon.com>
@ 2016-04-28 17:51 ` Geert Uytterhoeven
2016-04-28 17:58 ` Rich Felker
[not found] ` <20160428175843.GZ21636@brightrain.aerifal.cx>
2016-04-28 19:54 ` Sam Ravnborg
1 sibling, 2 replies; 11+ messages in thread
From: Geert Uytterhoeven @ 2016-04-28 17:51 UTC (permalink / raw)
To: George Spelvin
Cc: Andrew Morton, Peter Zijlstra, zengzhaoxiu, Rich Felker,
David S. Miller, Helge Deller, Ivan Kokshaysky, James Hogan,
James E.J. Bottomley, Jonas Bonn, Lennox Wu, Ley Foon Tan, alpha,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-m68k,
open list:METAG ARCHITECTURE, Linux MIPS Mailing List,
Parisc List, Linux-sh list
On Thu, Apr 28, 2016 at 6:48 PM, George Spelvin <linux@horizon.com> wrote:
> Another few comments:
>
> 1. Would ARCH_HAS_FAST_FFS involve fewer changes than CPU_NO_EFFICIENT_FFS?
No, as you want to _disable_ ARCH_HAS_FAST_FFS / _enable_
CPU_NO_EFFICIENT_FFS as soon as you're enabling support for a
CPU that doesn't support it.
Logical OR is easier in both the Kconfig and C preprocessor languages
than logical NAND.
E.g. in Kconfig, a CPU core not supporting it can just select
CPU_NO_EFFICIENT_FFS.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [patch V3] lib: GCD: add binary GCD algorithm
2016-04-28 17:51 ` Geert Uytterhoeven
@ 2016-04-28 17:58 ` Rich Felker
[not found] ` <20160428175843.GZ21636@brightrain.aerifal.cx>
1 sibling, 0 replies; 11+ messages in thread
From: Rich Felker @ 2016-04-28 17:58 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: George Spelvin, Andrew Morton, Peter Zijlstra, zengzhaoxiu,
David S. Miller, Helge Deller, Ivan Kokshaysky, James Hogan,
James E.J. Bottomley, Jonas Bonn, Lennox Wu, Ley Foon Tan, alpha,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-m68k,
open list:METAG ARCHITECTURE, Linux MIPS Mailing List,
Parisc List, Linux-sh list, Russell
On Thu, Apr 28, 2016 at 07:51:06PM +0200, Geert Uytterhoeven wrote:
> On Thu, Apr 28, 2016 at 6:48 PM, George Spelvin <linux@horizon.com> wrote:
> > Another few comments:
> >
> > 1. Would ARCH_HAS_FAST_FFS involve fewer changes than CPU_NO_EFFICIENT_FFS?
>
> No, as you want to _disable_ ARCH_HAS_FAST_FFS / _enable_
> CPU_NO_EFFICIENT_FFS as soon as you're enabling support for a
> CPU that doesn't support it.
>
> Logical OR is easier in both the Kconfig and C preprocessor languages
> than logical NAND.
>
> E.g. in Kconfig, a CPU core not supporting it can just select
> CPU_NO_EFFICIENT_FFS.
How does a CPU lack an efficient ffs/ctz anyway? There are all sorts
of ways to implement it without a native insn, some of which are
almost or just as fast as the native insn on cpus that have the
latter. On anything with a fast multiply, the de Bruijn sequence
approach is near-optimal, and otherwise one of the binary-search type
approaches (possibly branchless) can be used. If the compiler doesn't
generate an appropriate one for __builtin_ctz, that's arguably a
compiler bug.
Rich
^ permalink raw reply [flat|nested] 11+ messages in thread[parent not found: <20160428175843.GZ21636@brightrain.aerifal.cx>]
* Re: [patch V3] lib: GCD: add binary GCD algorithm
[not found] ` <20160428175843.GZ21636@brightrain.aerifal.cx>
@ 2016-04-28 18:11 ` Geert Uytterhoeven
2016-04-28 19:15 ` George Spelvin
1 sibling, 0 replies; 11+ messages in thread
From: Geert Uytterhoeven @ 2016-04-28 18:11 UTC (permalink / raw)
To: Rich Felker
Cc: George Spelvin, Andrew Morton, Peter Zijlstra, zengzhaoxiu,
David S. Miller, Helge Deller, Ivan Kokshaysky, James Hogan,
James E.J. Bottomley, Jonas Bonn, Lennox Wu, Ley Foon Tan, alpha,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-m68k,
open list:METAG ARCHITECTURE, Linux MIPS Mailing List,
Parisc List, Linux-sh list, Russell
On Thu, Apr 28, 2016 at 7:58 PM, Rich Felker <dalias@libc.org> wrote:
> On Thu, Apr 28, 2016 at 07:51:06PM +0200, Geert Uytterhoeven wrote:
>> On Thu, Apr 28, 2016 at 6:48 PM, George Spelvin <linux@horizon.com> wrote:
>> > Another few comments:
>> >
>> > 1. Would ARCH_HAS_FAST_FFS involve fewer changes than CPU_NO_EFFICIENT_FFS?
>>
>> No, as you want to _disable_ ARCH_HAS_FAST_FFS / _enable_
>> CPU_NO_EFFICIENT_FFS as soon as you're enabling support for a
>> CPU that doesn't support it.
>>
>> Logical OR is easier in both the Kconfig and C preprocessor languages
>> than logical NAND.
>>
>> E.g. in Kconfig, a CPU core not supporting it can just select
>> CPU_NO_EFFICIENT_FFS.
>
> How does a CPU lack an efficient ffs/ctz anyway? There are all sorts
> of ways to implement it without a native insn, some of which are
> almost or just as fast as the native insn on cpus that have the
> latter. On anything with a fast multiply, the de Bruijn sequence
> approach is near-optimal, and otherwise one of the binary-search type
> approaches (possibly branchless) can be used. If the compiler doesn't
> generate an appropriate one for __builtin_ctz, that's arguably a
> compiler bug.
m68k-linux-gcc 4.6.3 generates:
jsr __ctzsi2
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [patch V3] lib: GCD: add binary GCD algorithm
[not found] ` <20160428175843.GZ21636@brightrain.aerifal.cx>
2016-04-28 18:11 ` Geert Uytterhoeven
@ 2016-04-28 19:15 ` George Spelvin
1 sibling, 0 replies; 11+ messages in thread
From: George Spelvin @ 2016-04-28 19:15 UTC (permalink / raw)
To: dalias, geert
Cc: akpm, davem, deller, ink, james.hogan, jejb, jonas, lennox.wu,
lftan, linux-alpha, linux-arm-kernel, linux-kernel, linux-m68k,
linux-metag, linux-mips, linux-parisc, linux-sh, linux, linux,
linux, liqin.linux, mattst88, monstr, nios2-dev, peterz, ralf,
rth, sparclinux, uclinux-h8-devel, ysato, zengzhaoxiu,
zhaoxiu.zeng
> How does a CPU lack an efficient ffs/ctz anyway? There are all sorts
> of ways to implement it without a native insn, some of which are
> almost or just as fast as the native insn on cpus that have the
> latter. On anything with a fast multiply, the de Bruijn sequence
> approach is near-optimal, and otherwise one of the binary-search type
> approaches (possibly branchless) can be used. If the compiler doesn't
> generate an appropriate one for __builtin_ctz, that's arguably a
> compiler bug.
What's wanted here is something faster than any of those.
Yes, there's a simple constant-time branch-free implementation:
unsigned inline __attribute__((const))
hweight32(uint32_t x)
{
x -= (x >> 1) & 0x55555555;
x = ((x >> 2) & 0x33333333) + (x & 0x33333333);
x += x >> 4;
x &= 0x0f0f0f0f;
x += x >> 8;
x += x >> 16;
return x & 63;
}
unsigned inline __attribute__((const))
__ffs32(uint32_t x)
{
return hweight(~x & (x-1));
}
but if you work it through, that's about 19 instructions; a few more on
platforms without 32-bit immediates. The shift itself makes an even 20,
and there are a lot of sequential dependencies (I count a 17-op chain
including the shift) limiting execution time.
The de Bruijn hack reduces the length but adds a memory access for
the table lookup. (http://supertech.csail.mit.edu/papers/debruijn.pdf)
In the GCD code, the number to normalize is basically random, so the
normalization loop shifts an average of 1 bit. One bit half the time,
a second bit 1/4 of the time, etc.
(The posted code in the FAST_FFS case omits one guaranteed shift at the
end of the loop because the normalization code is constant-time.)
So "fast __ffs" basically means faster than *one* iteration of
"while (!(x & 1)) x >>= 1;".
In this case "fast" means cheaper than *one* unpredictable branch, which
is a very small handful of instructions.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [patch V3] lib: GCD: add binary GCD algorithm
[not found] ` <20160428164856.10120.qmail@ns.horizon.com>
2016-04-28 17:51 ` Geert Uytterhoeven
@ 2016-04-28 19:54 ` Sam Ravnborg
1 sibling, 0 replies; 11+ messages in thread
From: Sam Ravnborg @ 2016-04-28 19:54 UTC (permalink / raw)
To: George Spelvin
Cc: akpm, peterz, zengzhaoxiu, dalias, davem, deller, geert, ink,
james.hogan, jejb, jonas, lennox.wu, lftan, linux-alpha,
linux-arm-kernel, linux-kernel, linux-m68k, linux-metag,
linux-mips, linux-parisc, linux-sh, linux, liqin.linux, mattst88,
monstr, nios2-dev, ralf, rth, sparclinux, uclinux-h8-devel, ysato,
zhaoxiu.zeng
> __ffs on the available architectures:
> Alpha: sometimes (CONFIG_ALPHA_EV6, CONFIG_ALPHA_EV67)
> ARC: sometimes (!CONFIG_ISA_ARCOMPACT)
> ARM: sometimes (V5+)
> ARM64: NO, could be written using RBIT and CLZ
> AVR: yes
> Blackfin: NO, could be written using hweight()
> C6x: yes
> CRIS: NO
> FR-V: yes
> H8300: NO
> Hexagon: yes
> IA64: yes
> M32R: NO
> M68k: sometimes
> MetaG: NO
> Microblaze: NO
> MIPS: sometimes
> MN10300: yes
> OpenRISC: NO
> PA-RISC: NO? Interesting code, but I think it's a net loss.
> PowerPC: yes
> S390: sometimes (CONFIG_HAVE_MARCH_Z9_109_FEATURES)
> Score: NO
> SH: NO
> SPARC: NO
SPARC: sparc64: YES, sparc32: NO
Patch needs to be updated to refelct this.
Sam
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [patch V3] lib: GCD: add binary GCD algorithm
[not found] <1461843824-19853-1-git-send-email-zengzhaoxiu@163.com>
` (4 preceding siblings ...)
[not found] ` <20160428164856.10120.qmail@ns.horizon.com>
@ 2016-05-20 10:27 ` kbuild test robot
5 siblings, 0 replies; 11+ messages in thread
From: kbuild test robot @ 2016-05-20 10:27 UTC (permalink / raw)
To: zengzhaoxiu
Cc: kbuild-all, akpm, linux, peterz, Zhaoxiu Zeng, Richard Henderson,
Ivan Kokshaysky, Matt Turner, Russell King, Yoshinori Sato,
Geert Uytterhoeven, James Hogan, Michal Simek, Ralf Baechle,
Ley Foon Tan, Jonas Bonn, James E.J. Bottomley, Helge Deller,
Chen Liqin, Lennox Wu, Rich Felker, David S. Miller, linux-kernel,
linux-alpha, linux-arm-kernel, uclinux-h8-devel
[-- Attachment #1: Type: text/plain, Size: 8871 bytes --]
Hi,
[auto build test ERROR on v4.6-rc5]
[cannot apply to next-20160519]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/zengzhaoxiu-163-com/lib-GCD-add-binary-GCD-algorithm/20160428-195527
config: mips-jz4740 (attached as .config)
compiler: mips-linux-gnu-gcc (Debian 5.3.1-8) 5.3.1 20160205
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=mips
Note: the linux-review/zengzhaoxiu-163-com/lib-GCD-add-binary-GCD-algorithm/20160428-195527 HEAD 35e1a24e8fc3a5308b053ed3c744f02ec2a76820 builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
In file included from arch/mips/include/asm/bitops.h:21:0,
from include/linux/bitops.h:36,
from include/linux/kernel.h:10,
from include/asm-generic/bug.h:13,
from arch/mips/include/asm/bug.h:41,
from include/linux/bug.h:4,
from include/linux/page-flags.h:9,
from kernel/bounds.c:9:
arch/mips/include/asm/cpu-features.h:205:28: warning: "cpu_data" is not defined [-Wundef]
# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
^
arch/mips/include/asm/cpu-features.h:241:5: note: in expansion of macro 'cpu_has_mips32r6'
cpu_has_mips32r6 | cpu_has_mips64r1 | \
^
arch/mips/include/asm/cpu-features.h:289:25: note: in expansion of macro 'cpu_has_mips_r'
#define cpu_has_clo_clz cpu_has_mips_r
^
arch/mips/include/asm/cpu-features.h:291:6: note: in expansion of macro 'cpu_has_clo_clz'
#if !cpu_has_clo_clz
^
>> arch/mips/include/asm/cpu-features.h:205:36: error: token "[" is not valid in preprocessor expressions
# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
^
arch/mips/include/asm/cpu-features.h:241:5: note: in expansion of macro 'cpu_has_mips32r6'
cpu_has_mips32r6 | cpu_has_mips64r1 | \
^
arch/mips/include/asm/cpu-features.h:289:25: note: in expansion of macro 'cpu_has_mips_r'
#define cpu_has_clo_clz cpu_has_mips_r
^
arch/mips/include/asm/cpu-features.h:291:6: note: in expansion of macro 'cpu_has_clo_clz'
#if !cpu_has_clo_clz
^
make[2]: *** [kernel/bounds.s] Error 1
make[2]: Target '__build' not remade because of errors.
make[1]: *** [prepare0] Error 2
make[1]: Target 'prepare' not remade because of errors.
make: *** [sub-make] Error 2
vim +205 arch/mips/include/asm/cpu-features.h
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 199 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 200 #endif
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 201 #ifndef cpu_has_mips32r2
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 202 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 203 #endif
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 204 #ifndef cpu_has_mips32r6
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 @205 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 206 #endif
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 207 #ifndef cpu_has_mips64r1
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 208 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 209 #endif
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 210 #ifndef cpu_has_mips64r2
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 211 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 212 #endif
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 213 #ifndef cpu_has_mips64r6
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 214 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 215 #endif
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 216
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 217 /*
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 218 * Shortcuts ...
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 219 */
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 220 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 221 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 222 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 223
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 224 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 225 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 226 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 227 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 228
2d83fea7 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 229 #define cpu_has_mips_3_4_5_64_r2_r6 \
2d83fea7 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 230 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
2d83fea7 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 231 #define cpu_has_mips_4_5_64_r2_r6 \
2d83fea7 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 232 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \
2d83fea7 arch/mips/include/asm/cpu-features.h Maciej W. Rozycki 2015-04-03 233 cpu_has_mips_r2 | cpu_has_mips_r6)
08a07904 arch/mips/include/asm/cpu-features.h Ralf Baechle 2014-04-19 234
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 235 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 236 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 237 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
0401572a include/asm-mips/cpu-features.h Ralf Baechle 2005-12-09 238 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 239 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
c46b302b arch/mips/include/asm/cpu-features.h Ralf Baechle 2008-10-28 240 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 @241 cpu_has_mips32r6 | cpu_has_mips64r1 | \
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 242 cpu_has_mips64r2 | cpu_has_mips64r6)
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 243
34c56fc1 arch/mips/include/asm/cpu-features.h Leonid Yegoshin 2014-11-13 244 /* MIPSR2 and MIPSR6 have a lot of similarities */
:::::: The code at line 205 was first introduced by commit
:::::: 34c56fc1c167facc375d927687df0a3891d164ac MIPS: asm: cpu: Add MIPSR6 ISA definitions
:::::: TO: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
:::::: CC: Markos Chandras <markos.chandras@imgtec.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 18282 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread