* [PATCH v2 4/4] m68k/atari: fix SCC initialization for debug console
@ 2014-05-26 13:29 Finn Thain
2014-05-26 21:51 ` Michael Schmitz
0 siblings, 1 reply; 7+ messages in thread
From: Finn Thain @ 2014-05-26 13:29 UTC (permalink / raw)
To: Michael Schmitz; +Cc: Geert Uytterhoeven, linux-m68k
Fix SCC initialization for Atari as was previously fixed for Mac. It's
probably not practical to share more code but some attempt is made to
align the Mac and Atari variants.
Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
---
This patch needs testing on Atari. It can't be tested without editing
macro definitions to enable SCC debug output (which also means disabling
MFP debug output).
Changed in v2: drop the baud rate change
---
arch/m68k/kernel/head.S | 31 +++++++++++++++++++++----------
1 file changed, 21 insertions(+), 10 deletions(-)
Index: linux-m68k/arch/m68k/kernel/head.S
===================================================================
--- linux-m68k.orig/arch/m68k/kernel/head.S 2014-05-26 23:13:50.000000000 +1000
+++ linux-m68k/arch/m68k/kernel/head.S 2014-05-26 23:24:33.000000000 +1000
@@ -2722,6 +2722,7 @@ func_return get_new_page
#define MAC_USE_SCC_B /* Printer port */
#if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B)
+/* Initialisation table for SCC with 3.6864 MHz PCLK */
L(scc_initable_mac):
.byte 4,0x44 /* x16, 1 stopbit, no parity */
.byte 3,0xc0 /* receiver: 8 bpc */
@@ -2744,14 +2745,12 @@ L(scc_initable_mac):
#define USE_MFP
#if defined(USE_SCC_A) || defined(USE_SCC_B)
-#define USE_SCC
-/* Initialisation table for SCC */
-L(scc_initable):
- .byte 9,12 /* Reset */
+/* Initialisation table for SCC with 7.9872 MHz PCLK */
+/* PCLK == 8.0539 gives baud == 9680.1 */
+L(scc_initable_atari):
.byte 4,0x44 /* x16, 1 stopbit, no parity */
.byte 3,0xc0 /* receiver: 8 bpc */
.byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
- .byte 9,0 /* no interrupts */
.byte 10,0 /* NRZ */
.byte 11,0x50 /* use baud rate generator */
.byte 12,24,13,0 /* 9600 baud */
@@ -2800,7 +2799,7 @@ LMFP_UDR = 0xfffa2f
*/
/*
- * Initialize serial port hardware for 9600/8/1
+ * Initialize serial port hardware
*/
func_start serial_init,%d0/%d1/%a0/%a1
/*
@@ -2810,7 +2809,7 @@ func_start serial_init,%d0/%d1/%a0/%a1
* d0 = boot info offset
* CONFIG_ATARI
* a0 = address of SCC
- * a1 = Liobase address/address of scc_initable
+ * a1 = Liobase address/address of scc_initable_atari
* d0 = init data for serial port
* CONFIG_MAC
* a0 = address of SCC
@@ -2846,9 +2845,21 @@ func_start serial_init,%d0/%d1/%a0/%a1
moveb %a1@(LPSG_READ),%d0
bset #5,%d0
moveb %d0,%a1@(LPSG_WRITE)
-#elif defined(USE_SCC)
+#elif defined(USE_SCC_A) || defined(USE_SCC_B)
lea %a1@(LSCC_CTRL),%a0
- lea %pc@(L(scc_initable)),%a1
+ /* Reset SCC register pointer */
+ moveb %a0@,%d0
+ /* Reset SCC device: write register pointer then register value */
+ moveb #9,%a0@
+ moveb #0xc0,%a0@
+ /* Wait for 5 PCLK cycles, which is about 63 CPU cycles */
+ /* 5 / 7.9872 MHz = approx. 0.63 us = 63 / 100 MHz */
+ movel #32,%d0
+2:
+ subq #1,%d0
+ jne 2b
+ /* Initialize channel */
+ lea %pc@(L(scc_initable_atari)),%a1
2: moveb %a1@+,%d0
jmi 3f
moveb %d0,%a0@
@@ -3017,7 +3028,7 @@ func_start serial_putc,%d0/%d1/%a0/%a1
nop
bset #5,%d0
moveb %d0,%a1@(LPSG_WRITE)
-#elif defined(USE_SCC)
+#elif defined(USE_SCC_A) || defined(USE_SCC_B)
3: btst #2,%a1@(LSCC_CTRL)
jeq 3b
moveb %d0,%a1@(LSCC_DATA)
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 4/4] m68k/atari: fix SCC initialization for debug console
2014-05-26 13:29 [PATCH v2 4/4] m68k/atari: fix SCC initialization for debug console Finn Thain
@ 2014-05-26 21:51 ` Michael Schmitz
2014-05-27 2:31 ` Finn Thain
0 siblings, 1 reply; 7+ messages in thread
From: Michael Schmitz @ 2014-05-26 21:51 UTC (permalink / raw)
To: Finn Thain; +Cc: Geert Uytterhoeven, Linux/m68k
Hi Finn,
according to the old driver source, all Ataris except for the TT use a
3.672 MHz clock at RTxC[A,B] for both the 9600 and 38400 baud
settings. Most lower baud rates use the 8 MHz PCLK input.
Divisors are 24 (9600 baud) and 6 (38400 baud) in that case.
The TT uses that same arrangement on channel A, but something very
different on channel B - 307.2 kHz at RTxCB and 2.4576 MHz on TRxCB.
Divisors are 2 (using RTxCB) and 4 (using TRxCB), resepectively.
Adding all that in would complicate the code too much - let's settle
for a comment in the code to say SCC_B should not be used on the TT
without fixing the init table.
See page 1181 of the Profibuch - that corresponds well with the old
SCC driver source (can send that by PM should you need it).
Further comment inline.
Cheers,
Michael
On Tue, May 27, 2014 at 1:29 AM, Finn Thain <fthain@telegraphics.com.au> wrote:
>
> Fix SCC initialization for Atari as was previously fixed for Mac. It's
> probably not practical to share more code but some attempt is made to
> align the Mac and Atari variants.
>
> Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
>
> ---
> This patch needs testing on Atari. It can't be tested without editing
> macro definitions to enable SCC debug output (which also means disabling
> MFP debug output).
>
> Changed in v2: drop the baud rate change
>
> ---
> arch/m68k/kernel/head.S | 31 +++++++++++++++++++++----------
> 1 file changed, 21 insertions(+), 10 deletions(-)
>
> Index: linux-m68k/arch/m68k/kernel/head.S
> ===================================================================
> --- linux-m68k.orig/arch/m68k/kernel/head.S 2014-05-26 23:13:50.000000000 +1000
> +++ linux-m68k/arch/m68k/kernel/head.S 2014-05-26 23:24:33.000000000 +1000
> @@ -2722,6 +2722,7 @@ func_return get_new_page
> #define MAC_USE_SCC_B /* Printer port */
>
> #if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B)
> +/* Initialisation table for SCC with 3.6864 MHz PCLK */
> L(scc_initable_mac):
> .byte 4,0x44 /* x16, 1 stopbit, no parity */
> .byte 3,0xc0 /* receiver: 8 bpc */
> @@ -2744,14 +2745,12 @@ L(scc_initable_mac):
> #define USE_MFP
>
> #if defined(USE_SCC_A) || defined(USE_SCC_B)
> -#define USE_SCC
> -/* Initialisation table for SCC */
> -L(scc_initable):
> - .byte 9,12 /* Reset */
> +/* Initialisation table for SCC with 7.9872 MHz PCLK */
> +/* PCLK == 8.0539 gives baud == 9680.1 */
> +L(scc_initable_atari):
> .byte 4,0x44 /* x16, 1 stopbit, no parity */
> .byte 3,0xc0 /* receiver: 8 bpc */
> .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
> - .byte 9,0 /* no interrupts */
> .byte 10,0 /* NRZ */
> .byte 11,0x50 /* use baud rate generator */
> .byte 12,24,13,0 /* 9600 baud */
Would be 6 instead of 24 here for 38400, presumably?
> @@ -2800,7 +2799,7 @@ LMFP_UDR = 0xfffa2f
> */
>
> /*
> - * Initialize serial port hardware for 9600/8/1
> + * Initialize serial port hardware
> */
> func_start serial_init,%d0/%d1/%a0/%a1
> /*
> @@ -2810,7 +2809,7 @@ func_start serial_init,%d0/%d1/%a0/%a1
> * d0 = boot info offset
> * CONFIG_ATARI
> * a0 = address of SCC
> - * a1 = Liobase address/address of scc_initable
> + * a1 = Liobase address/address of scc_initable_atari
> * d0 = init data for serial port
> * CONFIG_MAC
> * a0 = address of SCC
> @@ -2846,9 +2845,21 @@ func_start serial_init,%d0/%d1/%a0/%a1
> moveb %a1@(LPSG_READ),%d0
> bset #5,%d0
> moveb %d0,%a1@(LPSG_WRITE)
> -#elif defined(USE_SCC)
> +#elif defined(USE_SCC_A) || defined(USE_SCC_B)
> lea %a1@(LSCC_CTRL),%a0
> - lea %pc@(L(scc_initable)),%a1
> + /* Reset SCC register pointer */
> + moveb %a0@,%d0
> + /* Reset SCC device: write register pointer then register value */
> + moveb #9,%a0@
> + moveb #0xc0,%a0@
> + /* Wait for 5 PCLK cycles, which is about 63 CPU cycles */
> + /* 5 / 7.9872 MHz = approx. 0.63 us = 63 / 100 MHz */
> + movel #32,%d0
> +2:
> + subq #1,%d0
> + jne 2b
> + /* Initialize channel */
> + lea %pc@(L(scc_initable_atari)),%a1
> 2: moveb %a1@+,%d0
> jmi 3f
> moveb %d0,%a0@
> @@ -3017,7 +3028,7 @@ func_start serial_putc,%d0/%d1/%a0/%a1
> nop
> bset #5,%d0
> moveb %d0,%a1@(LPSG_WRITE)
> -#elif defined(USE_SCC)
> +#elif defined(USE_SCC_A) || defined(USE_SCC_B)
> 3: btst #2,%a1@(LSCC_CTRL)
> jeq 3b
> moveb %d0,%a1@(LSCC_DATA)
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 4/4] m68k/atari: fix SCC initialization for debug console
2014-05-26 21:51 ` Michael Schmitz
@ 2014-05-27 2:31 ` Finn Thain
2014-05-27 2:57 ` Michael Schmitz
0 siblings, 1 reply; 7+ messages in thread
From: Finn Thain @ 2014-05-27 2:31 UTC (permalink / raw)
To: Michael Schmitz; +Cc: Geert Uytterhoeven, Linux/m68k
On Tue, 27 May 2014, Michael Schmitz wrote:
> Hi Finn,
>
> according to the old driver source, all Ataris except for the TT use a
> 3.672 MHz clock at RTxC[A,B] for both the 9600 and 38400 baud settings.
> Most lower baud rates use the 8 MHz PCLK input. Divisors are 24 (9600
> baud) and 6 (38400 baud) in that case.
>
Not quite (see below).
> The TT uses that same arrangement on channel A, but something very
> different on channel B - 307.2 kHz at RTxCB and 2.4576 MHz on TRxCB.
> Divisors are 2 (using RTxCB) and 4 (using TRxCB), resepectively.
>
TT aside, is it safe to assume in head.S that channel B is clocked the
same as channel A (i.e. 8 MHz)?
> Adding all that in would complicate the code too much - let's settle for
> a comment in the code to say SCC_B should not be used on the TT without
> fixing the init table.
A comment is probably a good idea but it can be a different patch. That
is, I'm happy for Geert to merge v2 unless you want to pursue 38400 baud.
> > 1 file changed, 21 insertions(+), 10 deletions(-)
> >
> > Index: linux-m68k/arch/m68k/kernel/head.S
> > ===================================================================
> > --- linux-m68k.orig/arch/m68k/kernel/head.S 2014-05-26 23:13:50.000000000 +1000
> > +++ linux-m68k/arch/m68k/kernel/head.S 2014-05-26 23:24:33.000000000 +1000
> > @@ -2722,6 +2722,7 @@ func_return get_new_page
> > #define MAC_USE_SCC_B /* Printer port */
> >
> > #if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B)
> > +/* Initialisation table for SCC with 3.6864 MHz PCLK */
> > L(scc_initable_mac):
> > .byte 4,0x44 /* x16, 1 stopbit, no parity */
> > .byte 3,0xc0 /* receiver: 8 bpc */
> > @@ -2744,14 +2745,12 @@ L(scc_initable_mac):
> > #define USE_MFP
> >
> > #if defined(USE_SCC_A) || defined(USE_SCC_B)
> > -#define USE_SCC
> > -/* Initialisation table for SCC */
> > -L(scc_initable):
> > - .byte 9,12 /* Reset */
> > +/* Initialisation table for SCC with 7.9872 MHz PCLK */
> > +/* PCLK == 8.0539 gives baud == 9680.1 */
> > +L(scc_initable_atari):
> > .byte 4,0x44 /* x16, 1 stopbit, no parity */
> > .byte 3,0xc0 /* receiver: 8 bpc */
> > .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
> > - .byte 9,0 /* no interrupts */
> > .byte 10,0 /* NRZ */
> > .byte 11,0x50 /* use baud rate generator */
> > .byte 12,24,13,0 /* 9600 baud */
>
> Would be 6 instead of 24 here for 38400, presumably?
>From http://linux-mac68k.cvs.sourceforge.net/viewvc/linux-mac68k/linux-mac68k/drivers/char/atari_SCC.c
351 For 8.053976 MHz == base 503374:
352 0 bps -> 0
353 50 bps -> 5032
354 75 bps -> 3354
355 110 bps -> 2286
356 134 bps -> 1876
357 150 bps -> 1676
358 200 bps -> 1256
359 300 bps -> 837
360 600 bps -> 417
361 1200 bps -> 208
362 1800 bps -> 138
363 2400 bps -> 103
364 4800 bps -> 50
365 9600 bps -> 24
366 19200 bps -> 11
367 31500 bps -> 6 (really 31461 bps)
368 50000 bps -> 3
369 125000 bps -> 0
Based on Baud = PCLK / (2 x mode x (Time Constant + 2)), we have:
mode 16 16 16 16 16 16
TC 6 11 24 1 4 10
PCLK 8.0539 8.0539 8.0539 3.670 3.670 3.670 MHz
baud 31460.5 19360.3 9680.2 38250.0 19125.0 9562.5
The x16 mode can't get close to 38400 baud. The first version of this
patch used the x1 mode:
mode 1 1 1
TC 102 102 103
PCLK 7.9872 8.0539 8.0539 MHz
baud 38400.0 38720.7 38351.9
I don't know why 38720.7 wasn't close enough to work when apparently
9680.2 baud does work.
Anyway, TC = 103 should be closer to 38400 baud given we now know PCLK is
8.0539 MHz, unless I'm missing something...
--
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 4/4] m68k/atari: fix SCC initialization for debug console
2014-05-27 2:31 ` Finn Thain
@ 2014-05-27 2:57 ` Michael Schmitz
2014-05-27 5:22 ` Finn Thain
0 siblings, 1 reply; 7+ messages in thread
From: Michael Schmitz @ 2014-05-27 2:57 UTC (permalink / raw)
To: Finn Thain; +Cc: Geert Uytterhoeven, Linux/m68k
Hi Finn,
On Tue, May 27, 2014 at 2:31 PM, Finn Thain <fthain@telegraphics.com.au> wrote:
>
> On Tue, 27 May 2014, Michael Schmitz wrote:
>
>> Hi Finn,
>>
>> according to the old driver source, all Ataris except for the TT use a
>> 3.672 MHz clock at RTxC[A,B] for both the 9600 and 38400 baud settings.
>> Most lower baud rates use the 8 MHz PCLK input. Divisors are 24 (9600
>> baud) and 6 (38400 baud) in that case.
>>
>
> Not quite (see below).
I see - so you are saying the head.S setup uses PCLK as clock source
in x16 mode, while the serial driver does something more complicated
to use the baud rate generator with a lower frequency clock?
>> The TT uses that same arrangement on channel A, but something very
>> different on channel B - 307.2 kHz at RTxCB and 2.4576 MHz on TRxCB.
>> Divisors are 2 (using RTxCB) and 4 (using TRxCB), resepectively.
>>
>
> TT aside, is it safe to assume in head.S that channel B is clocked the
> same as channel A (i.e. 8 MHz)?
That should be safe even for the TT with PCLK (PCLK is useable for
both channels).
>> Adding all that in would complicate the code too much - let's settle for
>> a comment in the code to say SCC_B should not be used on the TT without
>> fixing the init table.
>
> A comment is probably a good idea but it can be a different patch. That
> is, I'm happy for Geert to merge v2 unless you want to pursue 38400 baud.
Nope, not at this time. Not without seeing what the exact data rate is
with these new settings.
Cheers,
Michael
>> > 1 file changed, 21 insertions(+), 10 deletions(-)
>> >
>> > Index: linux-m68k/arch/m68k/kernel/head.S
>> > ===================================================================
>> > --- linux-m68k.orig/arch/m68k/kernel/head.S 2014-05-26 23:13:50.000000000 +1000
>> > +++ linux-m68k/arch/m68k/kernel/head.S 2014-05-26 23:24:33.000000000 +1000
>> > @@ -2722,6 +2722,7 @@ func_return get_new_page
>> > #define MAC_USE_SCC_B /* Printer port */
>> >
>> > #if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B)
>> > +/* Initialisation table for SCC with 3.6864 MHz PCLK */
>> > L(scc_initable_mac):
>> > .byte 4,0x44 /* x16, 1 stopbit, no parity */
>> > .byte 3,0xc0 /* receiver: 8 bpc */
>> > @@ -2744,14 +2745,12 @@ L(scc_initable_mac):
>> > #define USE_MFP
>> >
>> > #if defined(USE_SCC_A) || defined(USE_SCC_B)
>> > -#define USE_SCC
>> > -/* Initialisation table for SCC */
>> > -L(scc_initable):
>> > - .byte 9,12 /* Reset */
>> > +/* Initialisation table for SCC with 7.9872 MHz PCLK */
>> > +/* PCLK == 8.0539 gives baud == 9680.1 */
>> > +L(scc_initable_atari):
>> > .byte 4,0x44 /* x16, 1 stopbit, no parity */
>> > .byte 3,0xc0 /* receiver: 8 bpc */
>> > .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
>> > - .byte 9,0 /* no interrupts */
>> > .byte 10,0 /* NRZ */
>> > .byte 11,0x50 /* use baud rate generator */
>> > .byte 12,24,13,0 /* 9600 baud */
>>
>> Would be 6 instead of 24 here for 38400, presumably?
>
> From http://linux-mac68k.cvs.sourceforge.net/viewvc/linux-mac68k/linux-mac68k/drivers/char/atari_SCC.c
>
> 351 For 8.053976 MHz == base 503374:
> 352 0 bps -> 0
> 353 50 bps -> 5032
> 354 75 bps -> 3354
> 355 110 bps -> 2286
> 356 134 bps -> 1876
> 357 150 bps -> 1676
> 358 200 bps -> 1256
> 359 300 bps -> 837
> 360 600 bps -> 417
> 361 1200 bps -> 208
> 362 1800 bps -> 138
> 363 2400 bps -> 103
> 364 4800 bps -> 50
> 365 9600 bps -> 24
> 366 19200 bps -> 11
> 367 31500 bps -> 6 (really 31461 bps)
> 368 50000 bps -> 3
> 369 125000 bps -> 0
>
> Based on Baud = PCLK / (2 x mode x (Time Constant + 2)), we have:
>
> mode 16 16 16 16 16 16
> TC 6 11 24 1 4 10
> PCLK 8.0539 8.0539 8.0539 3.670 3.670 3.670 MHz
> baud 31460.5 19360.3 9680.2 38250.0 19125.0 9562.5
>
> The x16 mode can't get close to 38400 baud. The first version of this
> patch used the x1 mode:
>
> mode 1 1 1
> TC 102 102 103
> PCLK 7.9872 8.0539 8.0539 MHz
> baud 38400.0 38720.7 38351.9
>
> I don't know why 38720.7 wasn't close enough to work when apparently
> 9680.2 baud does work.
>
> Anyway, TC = 103 should be closer to 38400 baud given we now know PCLK is
> 8.0539 MHz, unless I'm missing something...
>
> --
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 4/4] m68k/atari: fix SCC initialization for debug console
2014-05-27 2:57 ` Michael Schmitz
@ 2014-05-27 5:22 ` Finn Thain
2014-05-27 7:55 ` Michael Schmitz
0 siblings, 1 reply; 7+ messages in thread
From: Finn Thain @ 2014-05-27 5:22 UTC (permalink / raw)
To: Michael Schmitz; +Cc: Geert Uytterhoeven, Linux/m68k
On Tue, 27 May 2014, Michael Schmitz wrote:
> so you are saying the head.S setup uses PCLK as clock source in x16
> mode, while the serial driver does something more complicated to use the
> baud rate generator with a lower frequency clock?
It seems so. The baud rate table in Atari_SCC.c defines both a clock
source and time constant (divisor) for each speed.
static BAUD_ENTRY bdtab_norm[20] = {
/* B0 */ { 0, 0 },
/* B50 */ { CLK_RTxC, 4590 },
/* B75 */ { CLK_RTxC, 3060 },
/* B110 */ { CLK_PCLK, 4576 },
/* B134 */ { CLK_PCLK, 3756 },
/* B150 */ { CLK_RTxC, 1530 },
/* B200 */ { CLK_PCLK, 2516 },
/* B300 */ { CLK_PCLK, 1678 },
/* B600 */ { CLK_PCLK, 838 },
/* B1200 */ { CLK_PCLK, 420 },
/* B1800 */ { CLK_PCLK, 280 },
/* B2400 */ { CLK_PCLK, 210 },
/* B4800 */ { CLK_RTxC, 48 },
/* B9600 */ { CLK_RTxC, 24 },
/* B19200 */ { CLK_RTxC, 12 },
/* B38400 */ { CLK_RTxC, 6 }, /* #15 spd_extra */
/* B57600 */ { CLK_RTxC, 4 }, /* #16 spd_hi */
/* B115200 */ { CLK_RTxC, 2 }, /* #17 spd_vhi */
/* B230400 */ { CLK_RTxC, 1 }, /* #18 spd_shi */
/* B460800 */ { 0, 0 } /* #19 spd_warp: Impossible */
};
The x16 mode is set by SCC_change_speed() when time constant == 1 or time
constant > 4 though I don't understand why that is.
Atari_SCC.c, for 38400 baud, in SCC_change_speed() essentially does,
AUX1_CTRL_REG = 0x44
CLK_CTRL_REG = 0x50
DPLL_CTRL_REG = 0x00
TIMER_LOW_REG = 1
TIMER_HIGH_REG = 0
DPLL_CTRL_REG = 0x01
That is, set the BRG clock source to RTxC pin and time constant to 1,
which would give 38250 baud for a 3.6720 MHz clock source.
Whereas, head.S for 9600 baud does something like this,
AUX1_CTRL_REG = 0x44
CLK_CTRL_REG = 0x50
TIMER_LOW_REG = 24
TIMER_HIGH_REG = 0
DPLL_CTRL_REG = 0x02
DPLL_CTRL_REG = 0x03
That is, set the BRG clock source to PCLK and time constant to 24, which
would give 9680.2 baud for a 8.0539 MHz clock source.
Problem: bdtab_norm[] above specifies { CLK_RTxC, 24 } for 9600 baud. This
doesn't make sense. Perhaps the logic in SCC_ioctl() in Atari_SCC.c fixes
it up for speeds specified by the user? Who knows.
--
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 4/4] m68k/atari: fix SCC initialization for debug console
2014-05-27 5:22 ` Finn Thain
@ 2014-05-27 7:55 ` Michael Schmitz
2014-05-27 13:20 ` Finn Thain
0 siblings, 1 reply; 7+ messages in thread
From: Michael Schmitz @ 2014-05-27 7:55 UTC (permalink / raw)
To: Finn Thain; +Cc: Geert Uytterhoeven, Linux/m68k
Hi Finn,
> On Tue, 27 May 2014, Michael Schmitz wrote:
>
>
>> so you are saying the head.S setup uses PCLK as clock source in x16
>> mode, while the serial driver does something more complicated to use the
>> baud rate generator with a lower frequency clock?
>>
>
> It seems so. The baud rate table in Atari_SCC.c defines both a clock
> source and time constant (divisor) for each speed.
>
> static BAUD_ENTRY bdtab_norm[20] = {
> /* B0 */ { 0, 0 },
> /* B50 */ { CLK_RTxC, 4590 },
> /* B75 */ { CLK_RTxC, 3060 },
> /* B110 */ { CLK_PCLK, 4576 },
> /* B134 */ { CLK_PCLK, 3756 },
> /* B150 */ { CLK_RTxC, 1530 },
> /* B200 */ { CLK_PCLK, 2516 },
> /* B300 */ { CLK_PCLK, 1678 },
> /* B600 */ { CLK_PCLK, 838 },
> /* B1200 */ { CLK_PCLK, 420 },
> /* B1800 */ { CLK_PCLK, 280 },
> /* B2400 */ { CLK_PCLK, 210 },
> /* B4800 */ { CLK_RTxC, 48 },
> /* B9600 */ { CLK_RTxC, 24 },
> /* B19200 */ { CLK_RTxC, 12 },
> /* B38400 */ { CLK_RTxC, 6 }, /* #15 spd_extra */
> /* B57600 */ { CLK_RTxC, 4 }, /* #16 spd_hi */
> /* B115200 */ { CLK_RTxC, 2 }, /* #17 spd_vhi */
> /* B230400 */ { CLK_RTxC, 1 }, /* #18 spd_shi */
> /* B460800 */ { 0, 0 } /* #19 spd_warp: Impossible */
> };
>
> The x16 mode is set by SCC_change_speed() when time constant == 1 or time
> constant > 4 though I don't understand why that is.
>
divisor (time constant) > 4 invokes the BRG setup logic instead of using
direct modes, and the divisor gets changed to (divisor/2) - 2. Probably
just a way to munge both direct and BRG modes into one simple table. I
didn't write the code :-)
> Atari_SCC.c, for 38400 baud, in SCC_change_speed() essentially does,
>
> AUX1_CTRL_REG = 0x44
> CLK_CTRL_REG = 0x50
> DPLL_CTRL_REG = 0x00
> TIMER_LOW_REG = 1
> TIMER_HIGH_REG = 0
> DPLL_CTRL_REG = 0x01
>
> That is, set the BRG clock source to RTxC pin and time constant to 1,
> which would give 38250 baud for a 3.6720 MHz clock source.
>
> Whereas, head.S for 9600 baud does something like this,
>
> AUX1_CTRL_REG = 0x44
> CLK_CTRL_REG = 0x50
> TIMER_LOW_REG = 24
> TIMER_HIGH_REG = 0
> DPLL_CTRL_REG = 0x02
> DPLL_CTRL_REG = 0x03
>
> That is, set the BRG clock source to PCLK and time constant to 24, which
> would give 9680.2 baud for a 8.0539 MHz clock source.
>
> Problem: bdtab_norm[] above specifies { CLK_RTxC, 24 } for 9600 baud. This
> doesn't make sense. Perhaps the logic in SCC_ioctl() in Atari_SCC.c fixes
> it up for speeds specified by the user? Who knows.
>
That ends up using time constant 10 and mode 16 as per your calculation
for 3.67 MHz clock input - 9562 baud instead of the 9680 possible from
the 8 MHz clock. I might have misunderstood something - would really
want to check that using a scope.
Both appear to work OK, so no matter really.
Cheers,
Michael
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 4/4] m68k/atari: fix SCC initialization for debug console
2014-05-27 7:55 ` Michael Schmitz
@ 2014-05-27 13:20 ` Finn Thain
0 siblings, 0 replies; 7+ messages in thread
From: Finn Thain @ 2014-05-27 13:20 UTC (permalink / raw)
To: Michael Schmitz; +Cc: Geert Uytterhoeven, Linux/m68k
On Tue, 27 May 2014, Michael Schmitz wrote:
> >
> > Problem: bdtab_norm[] above specifies { CLK_RTxC, 24 } for 9600 baud.
> > This doesn't make sense. Perhaps the logic in SCC_ioctl() in
> > Atari_SCC.c fixes it up for speeds specified by the user? Who knows.
> >
>
> That ends up using time constant 10 and mode 16 as per your calculation
> for 3.67 MHz clock input - 9562 baud instead of the 9680 possible from
> the 8 MHz clock.
Yes, I see now. This code is confusing.
> I might have misunderstood something - would really want to check that
> using a scope.
>
> Both appear to work OK, so no matter really.
And besides, there's no need to change the baud rate until someone
#defines USE_SCC_[AB] and then gets annoyed with 9600 baud.
--
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2014-05-27 13:21 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-05-26 13:29 [PATCH v2 4/4] m68k/atari: fix SCC initialization for debug console Finn Thain
2014-05-26 21:51 ` Michael Schmitz
2014-05-27 2:31 ` Finn Thain
2014-05-27 2:57 ` Michael Schmitz
2014-05-27 5:22 ` Finn Thain
2014-05-27 7:55 ` Michael Schmitz
2014-05-27 13:20 ` Finn Thain
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