[PATCH 0/7] dma: fsl/mcf-edma: Bug fixes and enhancements for ColdFire support

[PATCH 0/7] dma: fsl/mcf-edma: Bug fixes and enhancements for ColdFire support

[Jean-Michel Hautbois]

This series addresses several bugs in the fsl-edma and mcf-edma drivers
affecting MCF54418 ColdFire processors.

Patch 1 adds a write barrier after TCD descriptor fill to ensure proper
memory ordering.

Patch 2 adds the FSL_EDMA_DRV_MCF flag to fix byte-lane addressing for
MCF54418.

Patch 3 adds per-channel IRQ naming for easier debugging.

Patches 4-6 fix the interrupt and error handlers for all 64 DMA
channels:
- Patch 4 fixes the interrupt handler to process all 64 channels
- Patch 5 moves the error handler out of the header file for clarity
- Patch 6 fixes the error handler for all 64 channels with proper types

Patch 7 adds source stride support for interleaved DMA transfers,
enabling memory access patterns where source samples are not contiguous.

Tested on a custom MCF54418-based platform with slave DMA transfers.

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
Jean-Michel Hautbois (7):
      dma: fsl-edma: Add write barrier after TCD descriptor fill
      dma: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA
      dma: mcf-edma: Add per-channel IRQ naming for debugging
      dma: mcf-edma: Fix interrupt handler for 64 DMA channels
      dma: fsl-edma: Move error handler out of header file
      dma: mcf-edma: Fix error handler for all 64 DMA channels
      dma: fsl-edma: Support source stride for interleaved DMA transfers

 drivers/dma/fsl-edma-common.c | 14 +++++++++
 drivers/dma/fsl-edma-common.h | 11 ++++----
 drivers/dma/mcf-edma-main.c   | 66 +++++++++++++++++++++++++------------------
 3 files changed, 57 insertions(+), 34 deletions(-)
---
base-commit: d13f3ac64efb868d09cb2726b1e84929afe90235
change-id: 20251123-dma-coldfire-5f36aee143b3

Best regards,
-- 
Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>

[PATCH 1/7] dma: fsl-edma: Add write barrier after TCD descriptor fill

[Jean-Michel Hautbois]

Add dma_wmb() barrier after filling TCD descriptors to ensure all
descriptor writes are visible to the DMA engine before starting
transfers. This prevents potential race conditions where the DMA
hardware might read partially written descriptors.

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
 drivers/dma/fsl-edma-common.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 4976d7dde08090d16277af4b9f784b9745485320..db36a6aafc910364d75ce6c5d334fd19d2120b6b 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -553,6 +553,9 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
 	fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);
 
 	trace_edma_fill_tcd(fsl_chan, tcd);
+
+	/* Ensure descriptor writes are visible to DMA engine */
+	dma_wmb();
 }
 
 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,

-- 
2.39.5

Re: [PATCH 1/7] dma: fsl-edma: Add write barrier after TCD descriptor fill

[Frank Li]

On Mon, Nov 24, 2025 at 01:50:22PM +0100, Jean-Michel Hautbois wrote:
> Add dma_wmb() barrier after filling TCD descriptors to ensure all
> descriptor writes are visible to the DMA engine before starting
> transfers. This prevents potential race conditions where the DMA
> hardware might read partially written descriptors.
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> ---
>  drivers/dma/fsl-edma-common.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> index 4976d7dde08090d16277af4b9f784b9745485320..db36a6aafc910364d75ce6c5d334fd19d2120b6b 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -553,6 +553,9 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
>  	fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);
>
>  	trace_edma_fill_tcd(fsl_chan, tcd);
> +
> +	/* Ensure descriptor writes are visible to DMA engine */
> +	dma_wmb();

This is not necessary because there are writel() in
fsl_edma_issue_pending(), which will do memory barrier in writel().

currently, edma use vchan, descriptior have not dymantically to appending
to running queue. so writel() in fsl_edma_issue_pending() is enough.

Even though edma will support append to running queue in future, dma_wmd()
should be just before update csr.

 	dma_wmb();  // just before indicate TCD is ready to use.
	fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);

Frank
>  }
>
>  static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,
>
> --
> 2.39.5
>

Re: [PATCH 1/7] dma: fsl-edma: Add write barrier after TCD descriptor fill

[Jean-Michel Hautbois]

On Mon, Nov 24, 2025 at 10:57:49AM -0500, Frank Li wrote:
> On Mon, Nov 24, 2025 at 01:50:22PM +0100, Jean-Michel Hautbois wrote:
> > Add dma_wmb() barrier after filling TCD descriptors to ensure all
> > descriptor writes are visible to the DMA engine before starting
> > transfers. This prevents potential race conditions where the DMA
> > hardware might read partially written descriptors.
> >
> > Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> > ---
> >  drivers/dma/fsl-edma-common.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> > index 4976d7dde08090d16277af4b9f784b9745485320..db36a6aafc910364d75ce6c5d334fd19d2120b6b 100644
> > --- a/drivers/dma/fsl-edma-common.c
> > +++ b/drivers/dma/fsl-edma-common.c
> > @@ -553,6 +553,9 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
> >  	fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);
> >
> >  	trace_edma_fill_tcd(fsl_chan, tcd);
> > +
> > +	/* Ensure descriptor writes are visible to DMA engine */
> > +	dma_wmb();
> 
> This is not necessary because there are writel() in
> fsl_edma_issue_pending(), which will do memory barrier in writel().
> 
> currently, edma use vchan, descriptior have not dymantically to appending
> to running queue. so writel() in fsl_edma_issue_pending() is enough.
> 
> Even though edma will support append to running queue in future, dma_wmd()
> should be just before update csr.
> 
>  	dma_wmb();  // just before indicate TCD is ready to use.
> 	fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);
> 

Thanks for you detailed explanation, I will remove this commit from v2
:-).

JM
> Frank
> >  }
> >
> >  static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,
> >
> > --
> > 2.39.5
> >

[PATCH 2/7] dma: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA

[Jean-Michel Hautbois]

Add FSL_EDMA_DRV_MCF driver flag to identify MCF ColdFire eDMA
controllers which have a native M68K register layout.

The edma_writeb() function applies an XOR ^ 0x3 byte-lane adjustment for
big-endian eDMA controllers where byte registers within a 32-bit word
need address correction.

However, the MCF54418 eDMA 8-bit registers (SERQ, CERQ, SEEI, CEEI,
CINT, CERR, SSRT, CDNE) are located at sequential byte addresses
(0x4018-0x401F) as documented in the MCF54418 Reference Manual Table
19-2. No byte-lane adjustment is needed, as applying the XOR causes
writes to target incorrect registers (writing to CERR at 0x401D would
actually access SSRT at 0x401E).

Set this flag in the MCF eDMA driver to bypass the XOR adjustment and
access registers at their documented addresses.

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
 drivers/dma/fsl-edma-common.h | 5 ++++-
 drivers/dma/mcf-edma-main.c   | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 205a96489094805aa728b72a51ae101cd88fa003..4c86f2f39c1db9a812245fe85755ec8d1169c44c 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -225,6 +225,8 @@ struct fsl_edma_desc {
 #define FSL_EDMA_DRV_TCD64		BIT(15)
 /* All channel ERR IRQ share one IRQ line */
 #define FSL_EDMA_DRV_ERRIRQ_SHARE       BIT(16)
+/* MCF eDMA: Different register layout, no XOR for byte access */
+#define FSL_EDMA_DRV_MCF                BIT(17)
 
 
 #define FSL_EDMA_DRV_EDMA3	(FSL_EDMA_DRV_SPLIT_REG |	\
@@ -419,7 +421,8 @@ static inline void edma_writeb(struct fsl_edma_engine *edma,
 			       u8 val, void __iomem *addr)
 {
 	/* swap the reg offset for these in big-endian mode */
-	if (edma->big_endian)
+	/* MCF eDMA has different register layout, no XOR needed */
+	if (edma->big_endian && !(edma->drvdata->flags & FSL_EDMA_DRV_MCF))
 		iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
 	else
 		iowrite8(val, addr);
diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
index 9e1c6400c77be237684855759382d7b7bd2e6ea0..f95114829d8006fe4558169888ff38037d7610de 100644
--- a/drivers/dma/mcf-edma-main.c
+++ b/drivers/dma/mcf-edma-main.c
@@ -145,7 +145,7 @@ static void mcf_edma_irq_free(struct platform_device *pdev,
 }
 
 static struct fsl_edma_drvdata mcf_data = {
-	.flags = FSL_EDMA_DRV_EDMA64,
+	.flags = FSL_EDMA_DRV_EDMA64 | FSL_EDMA_DRV_MCF,
 	.setup_irq = mcf_edma_irq_init,
 };
 

-- 
2.39.5

Re: [PATCH 2/7] dma: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA

[Frank Li]

On Mon, Nov 24, 2025 at 01:50:23PM +0100, Jean-Michel Hautbois wrote:
> Add FSL_EDMA_DRV_MCF driver flag to identify MCF ColdFire eDMA
> controllers which have a native M68K register layout.
>
> The edma_writeb() function applies an XOR ^ 0x3 byte-lane adjustment for
> big-endian eDMA controllers where byte registers within a 32-bit word
> need address correction.
>
> However, the MCF54418 eDMA 8-bit registers (SERQ, CERQ, SEEI, CEEI,
> CINT, CERR, SSRT, CDNE) are located at sequential byte addresses
> (0x4018-0x401F) as documented in the MCF54418 Reference Manual Table
> 19-2. No byte-lane adjustment is needed, as applying the XOR causes
> writes to target incorrect registers (writing to CERR at 0x401D would
> actually access SSRT at 0x401E).
>
> Set this flag in the MCF eDMA driver to bypass the XOR adjustment and
> access registers at their documented addresses.
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/dma/fsl-edma-common.h | 5 ++++-
>  drivers/dma/mcf-edma-main.c   | 2 +-
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
> index 205a96489094805aa728b72a51ae101cd88fa003..4c86f2f39c1db9a812245fe85755ec8d1169c44c 100644
> --- a/drivers/dma/fsl-edma-common.h
> +++ b/drivers/dma/fsl-edma-common.h
> @@ -225,6 +225,8 @@ struct fsl_edma_desc {
>  #define FSL_EDMA_DRV_TCD64		BIT(15)
>  /* All channel ERR IRQ share one IRQ line */
>  #define FSL_EDMA_DRV_ERRIRQ_SHARE       BIT(16)
> +/* MCF eDMA: Different register layout, no XOR for byte access */
> +#define FSL_EDMA_DRV_MCF                BIT(17)
>
>
>  #define FSL_EDMA_DRV_EDMA3	(FSL_EDMA_DRV_SPLIT_REG |	\
> @@ -419,7 +421,8 @@ static inline void edma_writeb(struct fsl_edma_engine *edma,
>  			       u8 val, void __iomem *addr)
>  {
>  	/* swap the reg offset for these in big-endian mode */
> -	if (edma->big_endian)
> +	/* MCF eDMA has different register layout, no XOR needed */
> +	if (edma->big_endian && !(edma->drvdata->flags & FSL_EDMA_DRV_MCF))
>  		iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
>  	else
>  		iowrite8(val, addr);
> diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
> index 9e1c6400c77be237684855759382d7b7bd2e6ea0..f95114829d8006fe4558169888ff38037d7610de 100644
> --- a/drivers/dma/mcf-edma-main.c
> +++ b/drivers/dma/mcf-edma-main.c
> @@ -145,7 +145,7 @@ static void mcf_edma_irq_free(struct platform_device *pdev,
>  }
>
>  static struct fsl_edma_drvdata mcf_data = {
> -	.flags = FSL_EDMA_DRV_EDMA64,
> +	.flags = FSL_EDMA_DRV_EDMA64 | FSL_EDMA_DRV_MCF,
>  	.setup_irq = mcf_edma_irq_init,
>  };
>
>
> --
> 2.39.5
>

[PATCH 3/7] dma: mcf-edma: Add per-channel IRQ naming for debugging

[Jean-Michel Hautbois]

Add dynamic per-channel IRQ naming to make DMA interrupt identification
easier in /proc/interrupts and debugging tools.

Instead of all channels showing "eDMA", they now show:
- "eDMA-0" through "eDMA-15" for channels 0-15
- "eDMA-16" through "eDMA-55" for channels 16-55
- "eDMA-tx-56" for the shared channel 56-63 interrupt
- "eDMA-err" for the error interrupt

This aids debugging DMA issues by making it clear which channel's
interrupt is being serviced.

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
 drivers/dma/mcf-edma-main.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
index f95114829d8006fe4558169888ff38037d7610de..8a7c1787adb1f66f3b6729903635b072218afad1 100644
--- a/drivers/dma/mcf-edma-main.c
+++ b/drivers/dma/mcf-edma-main.c
@@ -81,8 +81,12 @@ static int mcf_edma_irq_init(struct platform_device *pdev,
 	if (!res)
 		return -1;
 
-	for (ret = 0, i = res->start; i <= res->end; ++i)
-		ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
+	for (ret = 0, i = res->start; i <= res->end; ++i) {
+		char *irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+						"eDMA-%d", i - res->start);
+
+		ret |= request_irq(i, mcf_edma_tx_handler, 0, irq_name, mcf_edma);
+	}
 	if (ret)
 		return ret;
 
@@ -91,15 +95,19 @@ static int mcf_edma_irq_init(struct platform_device *pdev,
 	if (!res)
 		return -1;
 
-	for (ret = 0, i = res->start; i <= res->end; ++i)
-		ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
+	for (ret = 0, i = res->start; i <= res->end; ++i) {
+		char *irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+						"eDMA-%d", 16 + i - res->start);
+
+		ret |= request_irq(i, mcf_edma_tx_handler, 0, irq_name, mcf_edma);
+	}
 	if (ret)
 		return ret;
 
 	ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
 	if (ret != -ENXIO) {
 		ret = request_irq(ret, mcf_edma_tx_handler,
-				  0, "eDMA", mcf_edma);
+				  0, "eDMA-tx-56", mcf_edma);
 		if (ret)
 			return ret;
 	}
@@ -107,7 +115,7 @@ static int mcf_edma_irq_init(struct platform_device *pdev,
 	ret = platform_get_irq_byname(pdev, "edma-err");
 	if (ret != -ENXIO) {
 		ret = request_irq(ret, mcf_edma_err_handler,
-				  0, "eDMA", mcf_edma);
+				  0, "eDMA-err", mcf_edma);
 		if (ret)
 			return ret;
 	}

-- 
2.39.5

Re: [PATCH 3/7] dma: mcf-edma: Add per-channel IRQ naming for debugging

[Geert Uytterhoeven]

Hi Jean-Michel,

On Mon, 24 Nov 2025 at 13:52, Jean-Michel Hautbois
<jeanmichel.hautbois@yoseli.org> wrote:
> Add dynamic per-channel IRQ naming to make DMA interrupt identification
> easier in /proc/interrupts and debugging tools.
>
> Instead of all channels showing "eDMA", they now show:
> - "eDMA-0" through "eDMA-15" for channels 0-15
> - "eDMA-16" through "eDMA-55" for channels 16-55
> - "eDMA-tx-56" for the shared channel 56-63 interrupt
> - "eDMA-err" for the error interrupt
>
> This aids debugging DMA issues by making it clear which channel's
> interrupt is being serviced.
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>

Thanks for your patch!

> --- a/drivers/dma/mcf-edma-main.c
> +++ b/drivers/dma/mcf-edma-main.c
> @@ -81,8 +81,12 @@ static int mcf_edma_irq_init(struct platform_device *pdev,
>         if (!res)
>                 return -1;
>
> -       for (ret = 0, i = res->start; i <= res->end; ++i)
> -               ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
> +       for (ret = 0, i = res->start; i <= res->end; ++i) {
> +               char *irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +                                               "eDMA-%d", i - res->start);

Can return NULL, so needs error handling.

> +
> +               ret |= request_irq(i, mcf_edma_tx_handler, 0, irq_name, mcf_edma);
> +       }
>         if (ret)
>                 return ret;
>
> @@ -91,15 +95,19 @@ static int mcf_edma_irq_init(struct platform_device *pdev,
>         if (!res)
>                 return -1;
>
> -       for (ret = 0, i = res->start; i <= res->end; ++i)
> -               ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
> +       for (ret = 0, i = res->start; i <= res->end; ++i) {
> +               char *irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> +                                               "eDMA-%d", 16 + i - res->start);

Likewise

> +
> +               ret |= request_irq(i, mcf_edma_tx_handler, 0, irq_name, mcf_edma);
> +       }
>         if (ret)
>                 return ret;
>
>         ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
>         if (ret != -ENXIO) {
>                 ret = request_irq(ret, mcf_edma_tx_handler,
> -                                 0, "eDMA", mcf_edma);
> +                                 0, "eDMA-tx-56", mcf_edma);

Fits on a single line.

>                 if (ret)
>                         return ret;
>         }
> @@ -107,7 +115,7 @@ static int mcf_edma_irq_init(struct platform_device *pdev,
>         ret = platform_get_irq_byname(pdev, "edma-err");
>         if (ret != -ENXIO) {
>                 ret = request_irq(ret, mcf_edma_err_handler,
> -                                 0, "eDMA", mcf_edma);
> +                                 0, "eDMA-err", mcf_edma);

Likewise.

>                 if (ret)
>                         return ret;
>         }
>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/7] dma: mcf-edma: Add per-channel IRQ naming for debugging

[kernel test robot]

Hi Jean-Michel,

kernel test robot noticed the following build warnings:

[auto build test WARNING on d13f3ac64efb868d09cb2726b1e84929afe90235]

url:    https://github.com/intel-lab-lkp/linux/commits/Jean-Michel-Hautbois/dma-fsl-edma-Add-write-barrier-after-TCD-descriptor-fill/20251124-205625
base:   d13f3ac64efb868d09cb2726b1e84929afe90235
patch link:    https://lore.kernel.org/r/20251124-dma-coldfire-v1-3-dc8f93185464%40yoseli.org
patch subject: [PATCH 3/7] dma: mcf-edma: Add per-channel IRQ naming for debugging
config: x86_64-buildonly-randconfig-002-20251125 (https://download.01.org/0day-ci/archive/20251125/202511251608.l7i5CNAr-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251125/202511251608.l7i5CNAr-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511251608.l7i5CNAr-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/dma/mcf-edma-main.c: In function 'mcf_edma_irq_init':
>> drivers/dma/mcf-edma-main.c:86:56: warning: format '%d' expects argument of type 'int', but argument 4 has type 'resource_size_t' {aka 'long long unsigned int'} [-Wformat=]
      86 |                                                 "eDMA-%d", i - res->start);
         |                                                       ~^   ~~~~~~~~~~~~~~
         |                                                        |     |
         |                                                        int   resource_size_t {aka long long unsigned int}
         |                                                       %lld
   drivers/dma/mcf-edma-main.c:100:56: warning: format '%d' expects argument of type 'int', but argument 4 has type 'resource_size_t' {aka 'long long unsigned int'} [-Wformat=]
     100 |                                                 "eDMA-%d", 16 + i - res->start);
         |                                                       ~^   ~~~~~~~~~~~~~~~~~~~
         |                                                        |          |
         |                                                        int        resource_size_t {aka long long unsigned int}
         |                                                       %lld


vim +86 drivers/dma/mcf-edma-main.c

    72	
    73	static int mcf_edma_irq_init(struct platform_device *pdev,
    74					struct fsl_edma_engine *mcf_edma)
    75	{
    76		int ret = 0, i;
    77		struct resource *res;
    78	
    79		res = platform_get_resource_byname(pdev,
    80					IORESOURCE_IRQ, "edma-tx-00-15");
    81		if (!res)
    82			return -1;
    83	
    84		for (ret = 0, i = res->start; i <= res->end; ++i) {
    85			char *irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
  > 86							"eDMA-%d", i - res->start);
    87	
    88			ret |= request_irq(i, mcf_edma_tx_handler, 0, irq_name, mcf_edma);
    89		}
    90		if (ret)
    91			return ret;
    92	
    93		res = platform_get_resource_byname(pdev,
    94				IORESOURCE_IRQ, "edma-tx-16-55");
    95		if (!res)
    96			return -1;
    97	
    98		for (ret = 0, i = res->start; i <= res->end; ++i) {
    99			char *irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
   100							"eDMA-%d", 16 + i - res->start);
   101	
   102			ret |= request_irq(i, mcf_edma_tx_handler, 0, irq_name, mcf_edma);
   103		}
   104		if (ret)
   105			return ret;
   106	
   107		ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
   108		if (ret != -ENXIO) {
   109			ret = request_irq(ret, mcf_edma_tx_handler,
   110					  0, "eDMA-tx-56", mcf_edma);
   111			if (ret)
   112				return ret;
   113		}
   114	
   115		ret = platform_get_irq_byname(pdev, "edma-err");
   116		if (ret != -ENXIO) {
   117			ret = request_irq(ret, mcf_edma_err_handler,
   118					  0, "eDMA-err", mcf_edma);
   119			if (ret)
   120				return ret;
   121		}
   122	
   123		return 0;
   124	}
   125	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 3/7] dma: mcf-edma: Add per-channel IRQ naming for debugging

[kernel test robot]

Hi Jean-Michel,

kernel test robot noticed the following build warnings:

[auto build test WARNING on d13f3ac64efb868d09cb2726b1e84929afe90235]

url:    https://github.com/intel-lab-lkp/linux/commits/Jean-Michel-Hautbois/dma-fsl-edma-Add-write-barrier-after-TCD-descriptor-fill/20251124-205625
base:   d13f3ac64efb868d09cb2726b1e84929afe90235
patch link:    https://lore.kernel.org/r/20251124-dma-coldfire-v1-3-dc8f93185464%40yoseli.org
patch subject: [PATCH 3/7] dma: mcf-edma: Add per-channel IRQ naming for debugging
config: x86_64-buildonly-randconfig-004-20251125 (https://download.01.org/0day-ci/archive/20251125/202511251902.QUkQzBbn-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251125/202511251902.QUkQzBbn-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511251902.QUkQzBbn-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/dma/mcf-edma-main.c:86:18: warning: format specifies type 'int' but the argument has type 'resource_size_t' (aka 'unsigned long long') [-Wformat]
      86 |                                                 "eDMA-%d", i - res->start);
         |                                                       ~~   ^~~~~~~~~~~~~~
         |                                                       %llu
   drivers/dma/mcf-edma-main.c:100:18: warning: format specifies type 'int' but the argument has type 'resource_size_t' (aka 'unsigned long long') [-Wformat]
     100 |                                                 "eDMA-%d", 16 + i - res->start);
         |                                                       ~~   ^~~~~~~~~~~~~~~~~~~
         |                                                       %llu
   2 warnings generated.


vim +86 drivers/dma/mcf-edma-main.c

    72	
    73	static int mcf_edma_irq_init(struct platform_device *pdev,
    74					struct fsl_edma_engine *mcf_edma)
    75	{
    76		int ret = 0, i;
    77		struct resource *res;
    78	
    79		res = platform_get_resource_byname(pdev,
    80					IORESOURCE_IRQ, "edma-tx-00-15");
    81		if (!res)
    82			return -1;
    83	
    84		for (ret = 0, i = res->start; i <= res->end; ++i) {
    85			char *irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
  > 86							"eDMA-%d", i - res->start);
    87	
    88			ret |= request_irq(i, mcf_edma_tx_handler, 0, irq_name, mcf_edma);
    89		}
    90		if (ret)
    91			return ret;
    92	
    93		res = platform_get_resource_byname(pdev,
    94				IORESOURCE_IRQ, "edma-tx-16-55");
    95		if (!res)
    96			return -1;
    97	
    98		for (ret = 0, i = res->start; i <= res->end; ++i) {
    99			char *irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
   100							"eDMA-%d", 16 + i - res->start);
   101	
   102			ret |= request_irq(i, mcf_edma_tx_handler, 0, irq_name, mcf_edma);
   103		}
   104		if (ret)
   105			return ret;
   106	
   107		ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
   108		if (ret != -ENXIO) {
   109			ret = request_irq(ret, mcf_edma_tx_handler,
   110					  0, "eDMA-tx-56", mcf_edma);
   111			if (ret)
   112				return ret;
   113		}
   114	
   115		ret = platform_get_irq_byname(pdev, "edma-err");
   116		if (ret != -ENXIO) {
   117			ret = request_irq(ret, mcf_edma_err_handler,
   118					  0, "eDMA-err", mcf_edma);
   119			if (ret)
   120				return ret;
   121		}
   122	
   123		return 0;
   124	}
   125	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH 4/7] dma: mcf-edma: Fix interrupt handler for 64 DMA channels

[Jean-Michel Hautbois]

Fix the DMA completion interrupt handler to properly handle all 64
channels on MCF54418 ColdFire processors.

The previous code used BIT(ch) to test interrupt status bits, which
causes undefined behavior on 32-bit architectures when ch >= 32 because
unsigned long is 32 bits and the shift would exceed the type width.

Replace with bitmap_from_u64() and for_each_set_bit() which correctly
handle 64-bit values on 32-bit systems by using a proper bitmap
representation.

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
 drivers/dma/mcf-edma-main.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
index 8a7c1787adb1f66f3b6729903635b072218afad1..dd64f50f2b0a70a4664b03c7d6a23e74c9bcd7ae 100644
--- a/drivers/dma/mcf-edma-main.c
+++ b/drivers/dma/mcf-edma-main.c
@@ -18,7 +18,8 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
 {
 	struct fsl_edma_engine *mcf_edma = dev_id;
 	struct edma_regs *regs = &mcf_edma->regs;
-	unsigned int ch;
+	unsigned long ch;
+	DECLARE_BITMAP(status_mask, 64);
 	u64 intmap;
 
 	intmap = ioread32(regs->inth);
@@ -27,11 +28,11 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
 	if (!intmap)
 		return IRQ_NONE;
 
-	for (ch = 0; ch < mcf_edma->n_chans; ch++) {
-		if (intmap & BIT(ch)) {
-			iowrite8(EDMA_MASK_CH(ch), regs->cint);
-			fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
-		}
+	bitmap_from_u64(status_mask, intmap);
+
+	for_each_set_bit(ch, status_mask, mcf_edma->n_chans) {
+		iowrite8(EDMA_MASK_CH(ch), regs->cint);
+		fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
 	}
 
 	return IRQ_HANDLED;

-- 
2.39.5

Re: [PATCH 4/7] dma: mcf-edma: Fix interrupt handler for 64 DMA channels

[Frank Li]

On Mon, Nov 24, 2025 at 01:50:25PM +0100, Jean-Michel Hautbois wrote:
> Fix the DMA completion interrupt handler to properly handle all 64
> channels on MCF54418 ColdFire processors.
>
> The previous code used BIT(ch) to test interrupt status bits, which
> causes undefined behavior on 32-bit architectures when ch >= 32 because
> unsigned long is 32 bits and the shift would exceed the type width.
>
> Replace with bitmap_from_u64() and for_each_set_bit() which correctly
> handle 64-bit values on 32-bit systems by using a proper bitmap
> representation.
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> ---
>  drivers/dma/mcf-edma-main.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
> index 8a7c1787adb1f66f3b6729903635b072218afad1..dd64f50f2b0a70a4664b03c7d6a23e74c9bcd7ae 100644
> --- a/drivers/dma/mcf-edma-main.c
> +++ b/drivers/dma/mcf-edma-main.c
> @@ -18,7 +18,8 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
>  {
>  	struct fsl_edma_engine *mcf_edma = dev_id;
>  	struct edma_regs *regs = &mcf_edma->regs;
> -	unsigned int ch;
> +	unsigned long ch;

channel number max value is 63. unsigned int should be enough.

Frank
> +	DECLARE_BITMAP(status_mask, 64);
>  	u64 intmap;
>
>  	intmap = ioread32(regs->inth);
> @@ -27,11 +28,11 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
>  	if (!intmap)
>  		return IRQ_NONE;
>
> -	for (ch = 0; ch < mcf_edma->n_chans; ch++) {
> -		if (intmap & BIT(ch)) {
> -			iowrite8(EDMA_MASK_CH(ch), regs->cint);
> -			fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
> -		}
> +	bitmap_from_u64(status_mask, intmap);
> +
> +	for_each_set_bit(ch, status_mask, mcf_edma->n_chans) {
> +		iowrite8(EDMA_MASK_CH(ch), regs->cint);
> +		fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
>  	}
>
>  	return IRQ_HANDLED;
>
> --
> 2.39.5
>

Re: [PATCH 4/7] dma: mcf-edma: Fix interrupt handler for 64 DMA channels

[Jean-Michel Hautbois]

Hi Frank,

On Mon, Nov 24, 2025 at 11:09:06AM -0500, Frank Li wrote:
> On Mon, Nov 24, 2025 at 01:50:25PM +0100, Jean-Michel Hautbois wrote:
> > Fix the DMA completion interrupt handler to properly handle all 64
> > channels on MCF54418 ColdFire processors.
> >
> > The previous code used BIT(ch) to test interrupt status bits, which
> > causes undefined behavior on 32-bit architectures when ch >= 32 because
> > unsigned long is 32 bits and the shift would exceed the type width.
> >
> > Replace with bitmap_from_u64() and for_each_set_bit() which correctly
> > handle 64-bit values on 32-bit systems by using a proper bitmap
> > representation.
> >
> > Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> > ---
> >  drivers/dma/mcf-edma-main.c | 13 +++++++------
> >  1 file changed, 7 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
> > index 8a7c1787adb1f66f3b6729903635b072218afad1..dd64f50f2b0a70a4664b03c7d6a23e74c9bcd7ae 100644
> > --- a/drivers/dma/mcf-edma-main.c
> > +++ b/drivers/dma/mcf-edma-main.c
> > @@ -18,7 +18,8 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
> >  {
> >  	struct fsl_edma_engine *mcf_edma = dev_id;
> >  	struct edma_regs *regs = &mcf_edma->regs;
> > -	unsigned int ch;
> > +	unsigned long ch;
> 
> channel number max value is 63. unsigned int should be enough.

Yes, indeed, it is enough. I changed to unsigned long because
for_each_set_bit() calls find_next_bit which returns unsigned long. This
only avoiding an implicit conversion. But I can remove this change if it
does not make sense ?

Thanks,
JM

> 
> Frank
> > +	DECLARE_BITMAP(status_mask, 64);
> >  	u64 intmap;
> >
> >  	intmap = ioread32(regs->inth);
> > @@ -27,11 +28,11 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
> >  	if (!intmap)
> >  		return IRQ_NONE;
> >
> > -	for (ch = 0; ch < mcf_edma->n_chans; ch++) {
> > -		if (intmap & BIT(ch)) {
> > -			iowrite8(EDMA_MASK_CH(ch), regs->cint);
> > -			fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
> > -		}
> > +	bitmap_from_u64(status_mask, intmap);
> > +
> > +	for_each_set_bit(ch, status_mask, mcf_edma->n_chans) {
> > +		iowrite8(EDMA_MASK_CH(ch), regs->cint);
> > +		fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
> >  	}
> >
> >  	return IRQ_HANDLED;
> >
> > --
> > 2.39.5
> >

Re: [PATCH 4/7] dma: mcf-edma: Fix interrupt handler for 64 DMA channels

[Frank Li]

On Tue, Nov 25, 2025 at 09:02:36AM +0100, Jean-Michel Hautbois wrote:
> Hi Frank,
>
> On Mon, Nov 24, 2025 at 11:09:06AM -0500, Frank Li wrote:
> > On Mon, Nov 24, 2025 at 01:50:25PM +0100, Jean-Michel Hautbois wrote:
> > > Fix the DMA completion interrupt handler to properly handle all 64
> > > channels on MCF54418 ColdFire processors.
> > >
> > > The previous code used BIT(ch) to test interrupt status bits, which
> > > causes undefined behavior on 32-bit architectures when ch >= 32 because
> > > unsigned long is 32 bits and the shift would exceed the type width.
> > >
> > > Replace with bitmap_from_u64() and for_each_set_bit() which correctly
> > > handle 64-bit values on 32-bit systems by using a proper bitmap
> > > representation.
> > >
> > > Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> > > ---
> > >  drivers/dma/mcf-edma-main.c | 13 +++++++------
> > >  1 file changed, 7 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
> > > index 8a7c1787adb1f66f3b6729903635b072218afad1..dd64f50f2b0a70a4664b03c7d6a23e74c9bcd7ae 100644
> > > --- a/drivers/dma/mcf-edma-main.c
> > > +++ b/drivers/dma/mcf-edma-main.c
> > > @@ -18,7 +18,8 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
> > >  {
> > >  	struct fsl_edma_engine *mcf_edma = dev_id;
> > >  	struct edma_regs *regs = &mcf_edma->regs;
> > > -	unsigned int ch;
> > > +	unsigned long ch;
> >
> > channel number max value is 63. unsigned int should be enough.
>
> Yes, indeed, it is enough. I changed to unsigned long because
> for_each_set_bit() calls find_next_bit which returns unsigned long. This
> only avoiding an implicit conversion. But I can remove this change if it
> does not make sense ?

It is not big deal. That's fine.

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>
> Thanks,
> JM
>
> >
> > Frank
> > > +	DECLARE_BITMAP(status_mask, 64);
> > >  	u64 intmap;
> > >
> > >  	intmap = ioread32(regs->inth);
> > > @@ -27,11 +28,11 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
> > >  	if (!intmap)
> > >  		return IRQ_NONE;
> > >
> > > -	for (ch = 0; ch < mcf_edma->n_chans; ch++) {
> > > -		if (intmap & BIT(ch)) {
> > > -			iowrite8(EDMA_MASK_CH(ch), regs->cint);
> > > -			fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
> > > -		}
> > > +	bitmap_from_u64(status_mask, intmap);
> > > +
> > > +	for_each_set_bit(ch, status_mask, mcf_edma->n_chans) {
> > > +		iowrite8(EDMA_MASK_CH(ch), regs->cint);
> > > +		fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
> > >  	}
> > >
> > >  	return IRQ_HANDLED;
> > >
> > > --
> > > 2.39.5
> > >

[PATCH 5/7] dma: fsl-edma: Move error handler out of header file

[Jean-Michel Hautbois]

Move fsl_edma_err_chan_handler from an inline function in the header
to a proper function in fsl-edma-common.c. This prepares for MCF
ColdFire eDMA support where the error handler needs to be called from
the MCF-specific error interrupt handler.

No functional change for existing users.

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
 drivers/dma/fsl-edma-common.c | 5 +++++
 drivers/dma/fsl-edma-common.h | 6 +-----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index db36a6aafc910364d75ce6c5d334fd19d2120b6b..40ac6a7d8480b9ed2c6a2bdec59b4fda5fcb6271 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -44,6 +44,11 @@
 #define EDMA64_ERRH		0x28
 #define EDMA64_ERRL		0x2c
 
+void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
+{
+	fsl_chan->status = DMA_ERROR;
+}
+
 void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan)
 {
 	spin_lock(&fsl_chan->vchan.lock);
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 4c86f2f39c1db9a812245fe85755ec8d1169c44c..64b537527291795964a77a9021192a39756b6987 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -478,11 +478,7 @@ static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
 	return container_of(vd, struct fsl_edma_desc, vdesc);
 }
 
-static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
-{
-	fsl_chan->status = DMA_ERROR;
-}
-
+void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan);
 void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,

-- 
2.39.5

Re: [PATCH 5/7] dma: fsl-edma: Move error handler out of header file

[Frank Li]

On Mon, Nov 24, 2025 at 01:50:26PM +0100, Jean-Michel Hautbois wrote:
> Move fsl_edma_err_chan_handler from an inline function in the header
> to a proper function in fsl-edma-common.c. This prepares for MCF
> ColdFire eDMA support where the error handler needs to be called from
> the MCF-specific error interrupt handler.
>
> No functional change for existing users.
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/dma/fsl-edma-common.c | 5 +++++
>  drivers/dma/fsl-edma-common.h | 6 +-----
>  2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> index db36a6aafc910364d75ce6c5d334fd19d2120b6b..40ac6a7d8480b9ed2c6a2bdec59b4fda5fcb6271 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -44,6 +44,11 @@
>  #define EDMA64_ERRH		0x28
>  #define EDMA64_ERRL		0x2c
>
> +void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
> +{
> +	fsl_chan->status = DMA_ERROR;
> +}
> +
>  void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan)
>  {
>  	spin_lock(&fsl_chan->vchan.lock);
> diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
> index 4c86f2f39c1db9a812245fe85755ec8d1169c44c..64b537527291795964a77a9021192a39756b6987 100644
> --- a/drivers/dma/fsl-edma-common.h
> +++ b/drivers/dma/fsl-edma-common.h
> @@ -478,11 +478,7 @@ static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
>  	return container_of(vd, struct fsl_edma_desc, vdesc);
>  }
>
> -static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
> -{
> -	fsl_chan->status = DMA_ERROR;
> -}
> -
> +void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan);
>  void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
>  void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
>  void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
>
> --
> 2.39.5
>

[PATCH 6/7] dma: mcf-edma: Fix error handler for all 64 DMA channels

[Jean-Michel Hautbois]

Fix the DMA error interrupt handler to properly handle errors on all
64 channels. The previous implementation had several issues:

1. Returned IRQ_NONE if low channels had no errors, even if high
   channels did
2. Used direct status assignment instead of fsl_edma_err_chan_handler()
   for high channels

Split the error handling into two separate loops for the low (0-31)
and high (32-63) channel groups, using for_each_set_bit() for cleaner
iteration. Both groups now consistently use fsl_edma_err_chan_handler()
for proper error status reporting.

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
 drivers/dma/mcf-edma-main.c | 31 ++++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
index dd64f50f2b0a70a4664b03c7d6a23e74c9bcd7ae..adae2914c23db3ce9244c0cb8d4208fd71874f76 100644
--- a/drivers/dma/mcf-edma-main.c
+++ b/drivers/dma/mcf-edma-main.c
@@ -12,6 +12,7 @@
 #include "fsl-edma-common.h"
 
 #define EDMA_CHANNELS		64
+#define EDMA_CHANS_PER_REG	(EDMA_CHANNELS / 2)
 #define EDMA_MASK_CH(x)		((x) & GENMASK(5, 0))
 
 static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
@@ -42,33 +43,33 @@ static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
 {
 	struct fsl_edma_engine *mcf_edma = dev_id;
 	struct edma_regs *regs = &mcf_edma->regs;
-	unsigned int err, ch;
+	unsigned int ch;
+	unsigned long err;
+	bool handled = false;
 
+	/* Check low 32 channels (0-31) */
 	err = ioread32(regs->errl);
-	if (!err)
-		return IRQ_NONE;
-
-	for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
-		if (err & BIT(ch)) {
+	if (err) {
+		handled = true;
+		for_each_set_bit(ch, &err, EDMA_CHANS_PER_REG) {
 			fsl_edma_disable_request(&mcf_edma->chans[ch]);
 			iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
 			fsl_edma_err_chan_handler(&mcf_edma->chans[ch]);
 		}
 	}
 
+	/* Check high 32 channels (32-63) */
 	err = ioread32(regs->errh);
-	if (!err)
-		return IRQ_NONE;
-
-	for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {
-		if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) {
-			fsl_edma_disable_request(&mcf_edma->chans[ch]);
-			iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
-			mcf_edma->chans[ch].status = DMA_ERROR;
+	if (err) {
+		handled = true;
+		for_each_set_bit(ch, &err, EDMA_CHANS_PER_REG) {
+			fsl_edma_disable_request(&mcf_edma->chans[ch + EDMA_CHANS_PER_REG]);
+			iowrite8(EDMA_CERR_CERR(ch + EDMA_CHANS_PER_REG), regs->cerr);
+			fsl_edma_err_chan_handler(&mcf_edma->chans[ch + EDMA_CHANS_PER_REG]);
 		}
 	}
 
-	return IRQ_HANDLED;
+	return handled ? IRQ_HANDLED : IRQ_NONE;
 }
 
 static int mcf_edma_irq_init(struct platform_device *pdev,

-- 
2.39.5

Re: [PATCH 6/7] dma: mcf-edma: Fix error handler for all 64 DMA channels

[Frank Li]

On Mon, Nov 24, 2025 at 01:50:27PM +0100, Jean-Michel Hautbois wrote:
> Fix the DMA error interrupt handler to properly handle errors on all
> 64 channels. The previous implementation had several issues:
>
> 1. Returned IRQ_NONE if low channels had no errors, even if high
>    channels did
> 2. Used direct status assignment instead of fsl_edma_err_chan_handler()
>    for high channels
>
> Split the error handling into two separate loops for the low (0-31)
> and high (32-63) channel groups, using for_each_set_bit() for cleaner
> iteration. Both groups now consistently use fsl_edma_err_chan_handler()
> for proper error status reporting.
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>

It is bug fix for high 32 channel. Need fix tags.

> ---
>  drivers/dma/mcf-edma-main.c | 31 ++++++++++++++++---------------
>  1 file changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
> index dd64f50f2b0a70a4664b03c7d6a23e74c9bcd7ae..adae2914c23db3ce9244c0cb8d4208fd71874f76 100644
> --- a/drivers/dma/mcf-edma-main.c
> +++ b/drivers/dma/mcf-edma-main.c
> @@ -12,6 +12,7 @@
>  #include "fsl-edma-common.h"
>
>  #define EDMA_CHANNELS		64
> +#define EDMA_CHANS_PER_REG	(EDMA_CHANNELS / 2)
                                ^ align to previous line

Frank

>  #define EDMA_MASK_CH(x)		((x) & GENMASK(5, 0))
>
>  static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
> @@ -42,33 +43,33 @@ static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
>  {
>  	struct fsl_edma_engine *mcf_edma = dev_id;
>  	struct edma_regs *regs = &mcf_edma->regs;
> -	unsigned int err, ch;
> +	unsigned int ch;
> +	unsigned long err;
> +	bool handled = false;
>
> +	/* Check low 32 channels (0-31) */
>  	err = ioread32(regs->errl);
> -	if (!err)
> -		return IRQ_NONE;
> -
> -	for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
> -		if (err & BIT(ch)) {
> +	if (err) {
> +		handled = true;
> +		for_each_set_bit(ch, &err, EDMA_CHANS_PER_REG) {
>  			fsl_edma_disable_request(&mcf_edma->chans[ch]);
>  			iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
>  			fsl_edma_err_chan_handler(&mcf_edma->chans[ch]);
>  		}
>  	}
>
> +	/* Check high 32 channels (32-63) */
>  	err = ioread32(regs->errh);
> -	if (!err)
> -		return IRQ_NONE;
> -
> -	for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {
> -		if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) {
> -			fsl_edma_disable_request(&mcf_edma->chans[ch]);
> -			iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
> -			mcf_edma->chans[ch].status = DMA_ERROR;
> +	if (err) {
> +		handled = true;
> +		for_each_set_bit(ch, &err, EDMA_CHANS_PER_REG) {
> +			fsl_edma_disable_request(&mcf_edma->chans[ch + EDMA_CHANS_PER_REG]);
> +			iowrite8(EDMA_CERR_CERR(ch + EDMA_CHANS_PER_REG), regs->cerr);
> +			fsl_edma_err_chan_handler(&mcf_edma->chans[ch + EDMA_CHANS_PER_REG]);
>  		}
>  	}
>
> -	return IRQ_HANDLED;
> +	return handled ? IRQ_HANDLED : IRQ_NONE;
>  }
>
>  static int mcf_edma_irq_init(struct platform_device *pdev,
>
> --
> 2.39.5
>

[PATCH 7/7] dma: fsl-edma: Support source stride for interleaved DMA transfers

[Jean-Michel Hautbois]

Add support for using src_port_window_size to configure the source
address stride (SOFF) in DMA transfers. This enables interleaved
memory access patterns needed for applications like stereo audio
de-interleaving.

When src_port_window_size is set, the source offset is calculated as:
  SOFF = src_port_window_size * dst_addr_width

This allows DMA to skip samples in memory while writing consecutive
samples to the device, enabling efficient stereo-to-mono de-interleaving
without CPU intervention.

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
 drivers/dma/fsl-edma-common.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 40ac6a7d8480b9ed2c6a2bdec59b4fda5fcb6271..e510cab24382fa557a2623465393c852b616fef3 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -647,6 +647,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
 			doff = fsl_chan->is_multi_fifo ? 4 : 0;
 			if (fsl_chan->cfg.dst_port_window_size)
 				doff = fsl_chan->cfg.dst_addr_width;
+			if (fsl_chan->cfg.src_port_window_size)
+				soff = fsl_chan->cfg.src_port_window_size *
+					fsl_chan->cfg.dst_addr_width;
 		} else if (direction == DMA_DEV_TO_MEM) {
 			src_addr = fsl_chan->dma_dev_addr;
 			dst_addr = dma_buf_next;
@@ -714,6 +717,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
 			dst_addr = fsl_chan->dma_dev_addr;
 			soff = fsl_chan->cfg.dst_addr_width;
 			doff = 0;
+			if (fsl_chan->cfg.src_port_window_size)
+				soff = fsl_chan->cfg.src_port_window_size *
+					fsl_chan->cfg.dst_addr_width;
 		} else if (direction == DMA_DEV_TO_MEM) {
 			src_addr = fsl_chan->dma_dev_addr;
 			dst_addr = sg_dma_address(sg);

-- 
2.39.5

Re: [PATCH 7/7] dma: fsl-edma: Support source stride for interleaved DMA transfers

[Frank Li]

On Mon, Nov 24, 2025 at 01:50:28PM +0100, Jean-Michel Hautbois wrote:
> Add support for using src_port_window_size to configure the source
> address stride (SOFF) in DMA transfers. This enables interleaved
> memory access patterns needed for applications like stereo audio
> de-interleaving.
>
> When src_port_window_size is set, the source offset is calculated as:
>   SOFF = src_port_window_size * dst_addr_width
>
> This allows DMA to skip samples in memory while writing consecutive
> samples to the device, enabling efficient stereo-to-mono de-interleaving
> without CPU intervention.

According to defination,

 * @src_port_window_size: The length of the register area in words the data need
 * to be accessed on the device side. It is only used for devices which is using
 * an area instead of a single register to receive the data. Typically the DMA
 * loops in this area in order to transfer the data.

src_port_window_size means the size of the region of continue memory.

It is wrong using src_port_window_size for your case, which want to skip
some memory.

But I think your user case is typical one. Maybe go through
struct dma_interleaved_template.

Frank
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> ---
>  drivers/dma/fsl-edma-common.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> index 40ac6a7d8480b9ed2c6a2bdec59b4fda5fcb6271..e510cab24382fa557a2623465393c852b616fef3 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -647,6 +647,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
>  			doff = fsl_chan->is_multi_fifo ? 4 : 0;
>  			if (fsl_chan->cfg.dst_port_window_size)
>  				doff = fsl_chan->cfg.dst_addr_width;
> +			if (fsl_chan->cfg.src_port_window_size)
> +				soff = fsl_chan->cfg.src_port_window_size *
> +					fsl_chan->cfg.dst_addr_width;
>  		} else if (direction == DMA_DEV_TO_MEM) {
>  			src_addr = fsl_chan->dma_dev_addr;
>  			dst_addr = dma_buf_next;
> @@ -714,6 +717,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
>  			dst_addr = fsl_chan->dma_dev_addr;
>  			soff = fsl_chan->cfg.dst_addr_width;
>  			doff = 0;
> +			if (fsl_chan->cfg.src_port_window_size)
> +				soff = fsl_chan->cfg.src_port_window_size *
> +					fsl_chan->cfg.dst_addr_width;
>  		} else if (direction == DMA_DEV_TO_MEM) {
>  			src_addr = fsl_chan->dma_dev_addr;
>  			dst_addr = sg_dma_address(sg);
>
> --
> 2.39.5
>