From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Sakari Ailus <sakari.ailus@linux.intel.com>
Cc: linux-media@vger.kernel.org, dongcheng.yan@intel.com
Subject: Re: [PATCH v3 08/11] media: ccs-pll: Add a flag for even PLL multipliers
Date: Thu, 24 Apr 2025 00:49:16 +0300 [thread overview]
Message-ID: <20250423214916.GA31282@pendragon.ideasonboard.com> (raw)
In-Reply-To: <20250423123359.1800904-9-sakari.ailus@linux.intel.com>
Hi Sakari,
Thank you for the patch.
On Wed, Apr 23, 2025 at 03:33:56PM +0300, Sakari Ailus wrote:
> Some devices (not entirely CCS compliant) only support even PLL
> multipliers. Add support for this through a PLL flag.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/ccs-pll.c | 11 ++++++++++-
> drivers/media/i2c/ccs-pll.h | 1 +
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
> index ebbc5e323244..f4be4e9f6777 100644
> --- a/drivers/media/i2c/ccs-pll.c
> +++ b/drivers/media/i2c/ccs-pll.c
> @@ -124,9 +124,10 @@ static void print_pll(struct device *dev, const struct ccs_pll *pll)
> dev_dbg(dev, "pixel rate on CSI-2 bus:\t%u\n",
> pll->pixel_rate_csi);
>
> - dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s%s\n",
> + dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s%s%s\n",
> pll->flags & PLL_FL(OP_PIX_CLOCK_PER_LANE) ? " op-pix-clock-per-lane" : "",
> pll->flags & PLL_FL(NO_OP_CLOCKS) ? " no-op-clocks" : "",
> + pll->flags & PLL_FL(EVEN_PLL_MULTIPLIER) ? " even-pll-multiplier" : "",
> pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
> pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
> " ext-ip-pll-divider" : "",
> @@ -312,6 +313,10 @@ __ccs_pll_calculate_vt_tree(struct device *dev,
> more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul);
> dev_dbg(dev, "more_mul2: %u\n", more_mul);
>
> + if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER &&
> + (mul & 1) && (more_mul & 1))
> + more_mul <<= 1;
> +
> pll_fr->pll_multiplier = mul * more_mul;
> if (pll_fr->pll_multiplier > lim_fr->max_pll_multiplier) {
> dev_dbg(dev, "pll multiplier %u too high\n",
> @@ -668,6 +673,10 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
> if (!is_one_or_even(i))
> i <<= 1;
>
> + if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER &&
> + mul & 1 && i & 1)
> + i <<= 1;
> +
> dev_dbg(dev, "final more_mul: %u\n", i);
> if (i > more_mul_max) {
> dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
> diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
> index ee206e5b287b..754eb5f52cc4 100644
> --- a/drivers/media/i2c/ccs-pll.h
> +++ b/drivers/media/i2c/ccs-pll.h
> @@ -22,6 +22,7 @@
> /* op pix clock is for all lanes in total normally */
> #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)
> #define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
> +#define CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER BIT(3)
> /* CCS PLL flags */
> #define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
I would probably have reordered the bits, but I don't mind much.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> #define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2025-04-23 21:49 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-23 12:33 [PATCH v3 00/11] CCS PLL fixes and improvements Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 01/11] media: ccs-pll: Start OP pre-PLL multiplier search from correct value Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 02/11] media: ccs-pll: Start VT " Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 03/11] media: ccs-pll: Check for too high VT PLL multiplier in dual PLL case Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 04/11] media: ccs-pll: Correct the upper limit of maximum op_pre_pll_clk_div Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 05/11] media: ccs-pll: Print a debug message on too high VT PLL OP clock Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 06/11] media: ccs-pll: Drop LINK_DECOUPLED flag Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 07/11] media: ccs-pll: Print missing PLL flags Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 08/11] media: ccs-pll: Add a flag for even PLL multipliers Sakari Ailus
2025-04-23 21:49 ` Laurent Pinchart [this message]
2025-04-23 12:33 ` [PATCH v3 09/11] media: ccs-pll: Better validate VT PLL branch Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 10/11] media: ccs-pll: Print PLL calculator flags in the beginning Sakari Ailus
2025-04-23 12:33 ` [PATCH v3 11/11] media: ccs-pll: Document the CCS PLL flags Sakari Ailus
2025-04-23 12:43 ` Laurent Pinchart
2025-04-23 12:51 ` Sakari Ailus
2025-04-23 15:37 ` [PATCH v4 " Sakari Ailus
2025-04-23 17:50 ` Laurent Pinchart
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250423214916.GA31282@pendragon.ideasonboard.com \
--to=laurent.pinchart@ideasonboard.com \
--cc=dongcheng.yan@intel.com \
--cc=linux-media@vger.kernel.org \
--cc=sakari.ailus@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox