From: Alexander Shiyan <eagle.alexander923@gmail.com>
To: linux-media@vger.kernel.org
Cc: Michael Riesch <michael.riesch@collabora.com>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Gerald Loacker <gerald.loacker@wolfvision.net>,
Dave Stevenson <dave.stevenson@raspberrypi.com>,
Alexander Shiyan <eagle.alexander923@gmail.com>
Subject: [PATCH v2 2/5] media: i2c: imx415: Add missing CSI-2 timing configurations for all lane rates
Date: Fri, 10 Apr 2026 09:19:41 +0300 [thread overview]
Message-ID: <20260410061944.241480-3-eagle.alexander923@gmail.com> (raw)
In-Reply-To: <20260410061944.241480-1-eagle.alexander923@gmail.com>
Add CSI-2 timing register configurations for lane rates 594 Mbps,
891 Mbps, 1782 Mbps, and 2079 Mbps.
Extend link_freq_menu_items to include these rates.
Reorder the existing mode entries in supported_modes[] to follow
ascending lane rate order.
These configurations are valid for both 2-lane and 4-lane operation
according to the datasheet.
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
drivers/media/i2c/imx415.c | 97 +++++++++++++++++++++++++++++++-------
1 file changed, 80 insertions(+), 17 deletions(-)
diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c
index 507a8c557ff1..b44d685360c1 100644
--- a/drivers/media/i2c/imx415.c
+++ b/drivers/media/i2c/imx415.c
@@ -109,8 +109,8 @@ static const char *const imx415_supply_names[] = {
* and converts them to link frequencies by a factor of two when needed.
*/
static const s64 link_freq_menu_items[] = {
- 594000000 / 2, 720000000 / 2, 891000000 / 2,
- 1440000000 / 2, 1485000000 / 2,
+ 594000000 / 2, 720000000 / 2, 891000000 / 2, 1440000000 / 2,
+ 1485000000 / 2, 1782000000 / 2, 2079000000 / 2, 2376000000 / 2,
};
struct imx415_clk_params {
@@ -453,6 +453,19 @@ static const struct imx415_clk_params imx415_clk_params[] = {
},
};
+/* 594 Mbps CSI configuration */
+static const struct cci_reg_sequence imx415_linkrate_594mbps[] = {
+ { IMX415_TCLKPOST, 0x0067 },
+ { IMX415_TCLKPREPARE, 0x0027 },
+ { IMX415_TCLKTRAIL, 0x0027 },
+ { IMX415_TCLKZERO, 0x00B7 },
+ { IMX415_THSPREPARE, 0x002F },
+ { IMX415_THSZERO, 0x004F },
+ { IMX415_THSTRAIL, 0x002F },
+ { IMX415_THSEXIT, 0x0047 },
+ { IMX415_TLPX, 0x0027 },
+};
+
/* 720 Mbps CSI configuration */
static const struct cci_reg_sequence imx415_linkrate_720mbps[] = {
{ IMX415_TCLKPOST, 0x006F },
@@ -466,6 +479,19 @@ static const struct cci_reg_sequence imx415_linkrate_720mbps[] = {
{ IMX415_TLPX, 0x0027 },
};
+/* 891 Mbps CSI configuration */
+static const struct cci_reg_sequence imx415_linkrate_891mbps[] = {
+ { IMX415_TCLKPOST, 0x007F },
+ { IMX415_TCLKPREPARE, 0x0037 },
+ { IMX415_TCLKTRAIL, 0x0037 },
+ { IMX415_TCLKZERO, 0x00F7 },
+ { IMX415_THSPREPARE, 0x003F },
+ { IMX415_THSZERO, 0x006F },
+ { IMX415_THSTRAIL, 0x003F },
+ { IMX415_THSEXIT, 0x005F },
+ { IMX415_TLPX, 0x002F },
+};
+
/* 1440 Mbps CSI configuration */
static const struct cci_reg_sequence imx415_linkrate_1440mbps[] = {
{ IMX415_TCLKPOST, 0x009F },
@@ -479,17 +505,30 @@ static const struct cci_reg_sequence imx415_linkrate_1440mbps[] = {
{ IMX415_TLPX, 0x004F },
};
-/* 891 Mbps CSI configuration */
-static const struct cci_reg_sequence imx415_linkrate_891mbps[] = {
- { IMX415_TCLKPOST, 0x007F },
- { IMX415_TCLKPREPARE, 0x0037 },
- { IMX415_TCLKTRAIL, 0x0037 },
- { IMX415_TCLKZERO, 0x00F7 },
- { IMX415_THSPREPARE, 0x003F },
- { IMX415_THSZERO, 0x006F },
- { IMX415_THSTRAIL, 0x003F },
- { IMX415_THSEXIT, 0x005F },
- { IMX415_TLPX, 0x002F },
+/* 1782 Mbps CSI configuration */
+static const struct cci_reg_sequence imx415_linkrate_1782mbps[] = {
+ { IMX415_TCLKPOST, 0x00B7 },
+ { IMX415_TCLKPREPARE, 0x0067 },
+ { IMX415_TCLKTRAIL, 0x006F },
+ { IMX415_TCLKZERO, 0x01DF },
+ { IMX415_THSPREPARE, 0x006F },
+ { IMX415_THSZERO, 0x00CF },
+ { IMX415_THSTRAIL, 0x006F },
+ { IMX415_THSEXIT, 0x00B7 },
+ { IMX415_TLPX, 0x005F },
+};
+
+/* 2079 Mbps CSI configuration */
+static const struct cci_reg_sequence imx415_linkrate_2079mbps[] = {
+ { IMX415_TCLKPOST, 0x00D7 },
+ { IMX415_TCLKPREPARE, 0x007F },
+ { IMX415_TCLKTRAIL, 0x007F },
+ { IMX415_TCLKZERO, 0x0237 },
+ { IMX415_THSPREPARE, 0x0087 },
+ { IMX415_THSZERO, 0x00EF },
+ { IMX415_THSTRAIL, 0x0087 },
+ { IMX415_THSEXIT, 0x00DF },
+ { IMX415_TLPX, 0x006F },
};
struct imx415_mode_reg_list {
@@ -505,6 +544,14 @@ struct imx415_mode {
/* mode configs */
static const struct imx415_mode supported_modes[] = {
+ {
+ .lane_rate = 594000000,
+ .hmax_min = { 3300, 1320 },
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(imx415_linkrate_594mbps),
+ .regs = imx415_linkrate_594mbps,
+ },
+ },
{
.lane_rate = 720000000,
.hmax_min = { 2032, 1066 },
@@ -513,6 +560,14 @@ static const struct imx415_mode supported_modes[] = {
.regs = imx415_linkrate_720mbps,
},
},
+ {
+ .lane_rate = 891000000,
+ .hmax_min = { 2200, 1100 },
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(imx415_linkrate_891mbps),
+ .regs = imx415_linkrate_891mbps,
+ },
+ },
{
.lane_rate = 1440000000,
.hmax_min = { 1066, 533 },
@@ -522,11 +577,19 @@ static const struct imx415_mode supported_modes[] = {
},
},
{
- .lane_rate = 891000000,
- .hmax_min = { 2200, 1100 },
+ .lane_rate = 1782000000,
+ .hmax_min = { 1100, 550 },
.reg_list = {
- .num_of_regs = ARRAY_SIZE(imx415_linkrate_891mbps),
- .regs = imx415_linkrate_891mbps,
+ .num_of_regs = ARRAY_SIZE(imx415_linkrate_1782mbps),
+ .regs = imx415_linkrate_1782mbps,
+ },
+ },
+ {
+ .lane_rate = 2079000000,
+ .hmax_min = { 1100, 550 },
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(imx415_linkrate_2079mbps),
+ .regs = imx415_linkrate_2079mbps,
},
},
};
--
2.52.0
next prev parent reply other threads:[~2026-04-10 6:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-10 6:19 [PATCH v2 0/5] media: i2c: imx415: driver improvements and fixes Alexander Shiyan
2026-04-10 6:19 ` [PATCH v2 1/5] media: i2c: imx415: Add missing ADBIT1 register for 10/12-bit output Alexander Shiyan
2026-04-10 6:19 ` Alexander Shiyan [this message]
2026-04-10 6:19 ` [PATCH v2 3/5] media: i2c: imx415: Add missing 4-lane CSI-2 timing configurations Alexander Shiyan
2026-04-10 6:19 ` [PATCH v2 4/5] media: i2c: imx415: Fix control handler initial count Alexander Shiyan
2026-04-10 6:19 ` [PATCH v2 5/5] media: i2c: imx415: Cluster horizontal and vertical flip controls Alexander Shiyan
2026-04-17 12:23 ` [PATCH v2 0/5] media: i2c: imx415: driver improvements and fixes Michael Riesch
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