From: Kate Hsuan <hpa@redhat.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>,
Hans de Goede <hansg@kernel.org>,
Hans Verkuil <hverkuil+cisco@kernel.org>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
Jai Luthra <jai.luthra@ideasonboard.com>
Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org,
Kate Hsuan <hpa@redhat.com>
Subject: [PATCH v2 2/3] media: i2c: imx471: Name the PLL registers in the OP domain
Date: Fri, 4 Sep 2026 15:51:12 +0800 [thread overview]
Message-ID: <20260904075113.125751-3-hpa@redhat.com> (raw)
In-Reply-To: <20260904075113.125751-1-hpa@redhat.com>
Define symbolic names for the registers in the OP domain, including
IMX471_REG_OP_PREPLLCK_DIV and IMX471_REG_OP_PLL_MULTIPLIER.Replaces
raw register addresses with meaningful macros to improve code readability.
Signed-off-by: Kate Hsuan <hpa@redhat.com>
---
drivers/media/i2c/imx471.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/media/i2c/imx471.c b/drivers/media/i2c/imx471.c
index 3c939f2a9056..316383076b3d 100644
--- a/drivers/media/i2c/imx471.c
+++ b/drivers/media/i2c/imx471.c
@@ -71,8 +71,17 @@
#define IMX471_REG_OPPXCK_DIV CCI_REG8(0x0309)
#define IMX471_REG_OPSYCK_DIV CCI_REG8(0x030b)
#define IMX471_REG_PLL_MULT_DRIV CCI_REG8(0x0310)
+#define IMX471_REG_OP_PREPLLCK_DIV CCI_REG16(0x030c)
+#define IMX471_REG_OP_MPY CCI_REG16(0x030e)
#define IMX471_PLL_SINGLE 0
#define IMX471_PLL_DUAL 1
+#define IMX471_VTPXCK_DIV 6
+#define IMX471_VTSYCK_DIV 2
+#define IMX471_PREPLLCK_VT_DIV 2
+#define IMX471_PLL_VT_MPY 121
+#define IMX471_OPSYCK_DIV 1
+#define IMX471_PLL_OP_MPY 83
+#define IMX471_PREPLLCK_OP_DIV 2
/* IMX471 native and active pixel array size */
#define IMX471_NATIVE_WIDTH 4672
@@ -233,14 +242,13 @@ static const struct cci_reg_sequence mode_1928x1088_regs[] = {
{ IMX471_REG_DIG_CROP_HEIGHT, 1088 },
{ IMX471_REG_X_OUTPUT_SIZE, 1928 },
{ IMX471_REG_Y_OUTPUT_SIZE, 1088 },
- { IMX471_REG_VTPXCK_DIV, 0x06 },
- { IMX471_REG_VTSYCK_DIV, 0x02 },
- { IMX471_REG_PREPLLCK_VT_DIV, 0x02 },
- { IMX471_REG_PLL_VT_MPY, 0x0079 },
- { IMX471_REG_OPSYCK_DIV, 0x01 },
- { CCI_REG8(0x030d), 0x02 },
- { CCI_REG8(0x030e), 0x00 },
- { CCI_REG8(0x030f), 0x53 },
+ { IMX471_REG_VTPXCK_DIV, IMX471_VTPXCK_DIV },
+ { IMX471_REG_VTSYCK_DIV, IMX471_VTSYCK_DIV },
+ { IMX471_REG_PREPLLCK_VT_DIV, IMX471_PREPLLCK_VT_DIV },
+ { IMX471_REG_PLL_VT_MPY, IMX471_PLL_VT_MPY },
+ { IMX471_REG_OPSYCK_DIV, IMX471_OPSYCK_DIV },
+ { IMX471_REG_OP_PREPLLCK_DIV, IMX471_PREPLLCK_OP_DIV },
+ { IMX471_REG_OP_MPY, IMX471_PLL_OP_MPY },
{ IMX471_REG_LINE_LENGTH_PCK, 2560 },
{ IMX471_REG_PLL_MULT_DRIV, IMX471_PLL_DUAL },
{ CCI_REG8(0x3f4c), 0x81 },
--
2.55.0
next prev parent reply other threads:[~2026-09-04 7:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 7:51 [PATCH v2 0/3] media: i2c: imx471: Add line length PCK setting and calculate pixel rate based on external clock rate Kate Hsuan
2026-09-04 7:51 ` [PATCH v2 1/3] media: i2c: imx471: Add line length PCK setting Kate Hsuan
2026-09-04 8:18 ` Sakari Ailus
2026-09-04 8:32 ` Sakari Ailus
2026-09-04 8:44 ` Kate Hsuan
2026-09-04 7:51 ` Kate Hsuan [this message]
2026-09-04 7:51 ` [PATCH v2 3/3] media: i2c: imx471: Calculate pixel rate based on external clock rate Kate Hsuan
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