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From: Kate Hsuan <hpa@redhat.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>,
	Hans de Goede <hansg@kernel.org>,
	Hans Verkuil <hverkuil+cisco@kernel.org>,
	Sakari Ailus <sakari.ailus@linux.intel.com>,
	Jai Luthra <jai.luthra@ideasonboard.com>
Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org,
	Kate Hsuan <hpa@redhat.com>
Subject: [PATCH v2 3/3] media: i2c: imx471: Calculate pixel rate based on external clock rate
Date: Fri,  4 Sep 2026 15:51:13 +0800	[thread overview]
Message-ID: <20260904075113.125751-4-hpa@redhat.com> (raw)
In-Reply-To: <20260904075113.125751-1-hpa@redhat.com>

The IMX471 sensor operates in PLL Dual Mode, so OP domain configurations
must be used to determine the pixel rate. Based on the IMX471 clock tree
topology, the pixel rate is calculated as:

(extclk * IOP_PLL_MPY * DDR_FACTOR) / (IOP_PREPLLCK_DIV * IOP_SYNCK_DIV * BPP)

With the register values, this yields a pixel rate of 159.36 MPix/s.

Signed-off-by: Kate Hsuan <hpa@redhat.com>
---
 drivers/media/i2c/imx471.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/media/i2c/imx471.c b/drivers/media/i2c/imx471.c
index 316383076b3d..d81d64dd8761 100644
--- a/drivers/media/i2c/imx471.c
+++ b/drivers/media/i2c/imx471.c
@@ -701,8 +701,17 @@ static int imx471_init_controls(struct imx471 *sensor)
 					   0,
 					   link_freq_menu_items);
 
-	/* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
-	pixel_rate = div_u64(IMX471_LINK_FREQ_DEFAULT * 2 * 4, 10);
+	/*
+	 * The sensor runs in the PLL DUAL mode so the configurations of the
+	 * OP domain are considered. According to the imx471 clock tree,
+	 * the pixel rate can be calculated as follows:
+	 * (exck_freq * IOP_PLL_MPY * DDR factor) /
+	 * (IOP_PREPLLCK_DIV * IOP_SYNCK_DIV * RAW10 bits) = 159.36 MPix/s
+	 */
+	pixel_rate = (IMX471_EXT_CLK * IMX471_PLL_OP_MPY * (u64)2) /
+		     (IMX471_PREPLLCK_OP_DIV * IMX471_OPSYCK_DIV * (u64)10);
+
+	dev_dbg(sensor->dev, "pixel_rate: %llu\n", pixel_rate);
 
 	v4l2_ctrl_new_std(ctrl_hdlr, &imx471_ctrl_ops,
 			  V4L2_CID_PIXEL_RATE, pixel_rate,
-- 
2.55.0


      parent reply	other threads:[~2026-09-04  7:52 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-04  7:51 [PATCH v2 0/3] media: i2c: imx471: Add line length PCK setting and calculate pixel rate based on external clock rate Kate Hsuan
2026-09-04  7:51 ` [PATCH v2 1/3] media: i2c: imx471: Add line length PCK setting Kate Hsuan
2026-09-04  8:18   ` Sakari Ailus
2026-09-04  8:32     ` Sakari Ailus
2026-09-04  8:44       ` Kate Hsuan
2026-09-04  7:51 ` [PATCH v2 2/3] media: i2c: imx471: Name the PLL registers in the OP domain Kate Hsuan
2026-09-04  7:51 ` Kate Hsuan [this message]

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