[PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY for X1E80100

[PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY for X1E80100

[George Neacsu via B4 Relay]

Hi Bryan, Vinod, David,

The Snapdragon Surface Pro 11's front camera, an IMX681, is on CSIPHY2
over one MIPI C-PHY trio. linux-next has the CSI2 PHY driver and the CAMSS
PHY API path, and C-PHY is the piece still missing for this camera. This
series adds the PHY side:

1. PHY_MODE_MIPI_CPHY and C-PHY configuration options in the generic PHY
   framework, because CAMSS had no way to ask the PHY for C-PHY;
2. C-PHY configuration helpers, the analogue of
   phy_mipi_dphy_get_default_config_for_hsclk();
3. a rename of the D-PHY init sequence in qcom-mipi-csi2;
4. lane mask and lane polarity helpers in qcom-mipi-csi2, with no
   functional change;
5. fsleep() for the init sequence delays, the same udelay() for the
   current D-PHY sequence;
6. C-PHY in qcom-mipi-csi2, with the X1E80100 sequence taken from
   Qualcomm's GPL-2.0 downstream header.

The series is on next-20261015 and applies there on its own. The two
CAMSS patches that use it build on David's "media: camss: Add support
for C-PHY configuration on Qualcomm platforms" v9, which is not in
linux-next yet, so I will send them on top of David's series:
https://lore.kernel.org/all/20260729-qcom-cphy-v9-0-1f8d9fdab037@ixit.cz/

Tested on the Surface Pro 11 (X1E80100), booting next-20261015 with this
series, David's v9 and those two CAMSS patches on top, with CSI2 PHY
nodes as in Bryan's x1e80100 camera DT v7, CAMSS in PHY API mode, and raw
capture over RDI:
- front IMX681 (Sergey's and Andre's v8 driver plus its C-PHY RFC) on
  CSIPHY2, one C-PHY trio at 2.4 Gsym/s: 3844x2640 at 30 fps, and the
  sensor's colour bars are byte-identical to the pattern captured with an
  out-of-tree driver. The settle count is computed, 28 at a 400 MHz
  timer;
- rear OV13858 on CSIPHY1, four D-PHY lanes: 29.9 fps.
On the earlier test setup, linux-next's CAMSS and CSI2 PHY as modules on
7.1.5, forcing any settle count from 6 to 48 gave the same frames.

Open question, from Nihal: the X1E table is Qualcomm's 2.5 Gsps one, and
downstream picks C-PHY settings by symbol rate. I would keep a single
table here and add selection by rate when a second rate is needed,
unless you would rather have the structure now.

Thanks,
George

---
Changes in v3:
- Drop the RFC prefix (Bryan)
- Test on a linux-next kernel instead of linux-next's modules on 7.1.5
  (Bryan)
- phy: u64 and u8 in struct phy_configure_opts_mipi_cphy and the
  helpers (sashiko); pick up Reviewed-by tags from Loic and Bryan
- qcom-mipi-csi2: split the lane mask and polarity helpers and the
  fsleep() change out of the C-PHY patch, each with no functional change
  for D-PHY
- qcom-mipi-csi2: write the C-PHY per-trio register addresses with
  CSIPHY_LN_CTRLn(); the object code is unchanged (David)
- Link to v2: https://lore.kernel.org/r/20261016-x1e-cphy-rfc-v2-0-377654253193@gmail.com

Changes in v2:
- Rebase on next-20261015, PHY patches only; the CAMSS patches follow
  David's series (Bryan)
- phy: rename lanes to trios (Loic), make symbol_rate unsigned long long
  so 32-bit can hold rates above 4.29 Gsym/s, and keep Bryan's R-b for
  that patch
- phy: new patch with the C-PHY helpers (Bryan, Loic)
- qcom-mipi-csi2: new patch renaming init_seq/lane_array_size to
  dphy_init_seq/dphy_lane_array_size (Bryan)
- qcom-mipi-csi2: rename the C-PHY table to lane_regs_v2_1_2_cphy and
  shorten its comment (Konrad)
- qcom-mipi-csi2: no separate bus_type; the endpoint sets phy_mode and
  set_mode() checks against it (Nihal)
- qcom-mipi-csi2: if/else instead of the ternaries, one declaration per
  line, and lanes_enable() split into lane mask and polarity helpers
  instead of the goto (Bryan, Nihal)
- qcom-mipi-csi2: configure() uses the helpers and keeps the link
  frequency, so clocks scale as for D-PHY
- qcom-mipi-csi2: compute the C-PHY settle count instead of the fixed
  table value; blank lines between the per-trio blocks; fsleep() for the
  sequence delays (Nihal)
- qcom-mipi-csi2: drop the video-interfaces.h include, no longer needed
- Link to v1: https://lore.kernel.org/r/20261015-x1e-cphy-rfc-v1-0-1f3fa9af940a@gmail.com

---
George Neacsu (6):
      phy: Add MIPI C-PHY mode and configuration options
      phy: Add MIPI C-PHY configuration helpers
      phy: qcom-mipi-csi2: Rename the D-PHY init sequence
      phy: qcom-mipi-csi2: Add lane mask and lane polarity helpers
      phy: qcom-mipi-csi2: Use fsleep() for init sequence delays
      phy: qcom-mipi-csi2: Add C-PHY support for X1E80100

 drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 228 ++++++++++++++++++---
 drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c     |  53 ++++-
 drivers/phy/qualcomm/phy-qcom-mipi-csi2.h          |   6 +-
 include/linux/phy/phy-mipi-cphy.h                  |  89 ++++++++
 include/linux/phy/phy.h                            |   5 +
 5 files changed, 348 insertions(+), 33 deletions(-)
---
base-commit: b810335a0699d1810683796b0e3ffe8827ddfe6c
change-id: 20261015-x1e-cphy-rfc-201860c8097f

Best regards,
-- 
George Neacsu <geocausa@gmail.com>

[PATCH v3 1/6] phy: Add MIPI C-PHY mode and configuration options

[George Neacsu via B4 Relay]

From: George Neacsu <geocausa@gmail.com>

The generic PHY framework has a mode and configuration options for MIPI
D-PHY but none for C-PHY, so a CSI-2 receiver has no way to ask a PHY
that does both for C-PHY. Add PHY_MODE_MIPI_CPHY and struct
phy_configure_opts_mipi_cphy. The options are the two values a receiver
knows: the symbol rate on each trio and the number of trios.

The first user is the Qualcomm CSI2 PHY, whose X1E80100 instances carry
the C-PHY front camera of the Surface Pro 11.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: George Neacsu <geocausa@gmail.com>
---
 include/linux/phy/phy-mipi-cphy.h | 29 +++++++++++++++++++++++++++++
 include/linux/phy/phy.h           |  5 +++++
 2 files changed, 34 insertions(+)

diff --git a/include/linux/phy/phy-mipi-cphy.h b/include/linux/phy/phy-mipi-cphy.h
new file mode 100644
index 0000000000..9b748d577b
--- /dev/null
+++ b/include/linux/phy/phy-mipi-cphy.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __PHY_MIPI_CPHY_H_
+#define __PHY_MIPI_CPHY_H_
+
+#include <linux/types.h>
+
+/**
+ * struct phy_configure_opts_mipi_cphy - MIPI C-PHY configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * MIPI C-PHY phy.
+ */
+struct phy_configure_opts_mipi_cphy {
+	/**
+	 * @symbol_rate:
+	 *
+	 * Symbol rate on each trio, in symbols per second.
+	 */
+	u64			symbol_rate;
+
+	/**
+	 * @trios:
+	 *
+	 * Number of active trios.
+	 */
+	u8			trios;
+};
+
+#endif /* __PHY_MIPI_CPHY_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index c480d6cb42..f123378340 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -19,6 +19,7 @@
 #include <linux/phy/phy-dp.h>
 #include <linux/phy/phy-hdmi.h>
 #include <linux/phy/phy-lvds.h>
+#include <linux/phy/phy-mipi-cphy.h>
 #include <linux/phy/phy-mipi-dphy.h>
 #include <linux/phy/phy-thunderbolt.h>
 
@@ -42,6 +43,7 @@ enum phy_mode {
 	PHY_MODE_PCIE,
 	PHY_MODE_ETHERNET,
 	PHY_MODE_MIPI_DPHY,
+	PHY_MODE_MIPI_CPHY,
 	PHY_MODE_SATA,
 	PHY_MODE_LVDS,
 	PHY_MODE_DP,
@@ -69,6 +71,8 @@ union phy_notify {
  *
  * @mipi_dphy:	Configuration set applicable for phys supporting
  *		the MIPI_DPHY phy mode.
+ * @mipi_cphy:	Configuration set applicable for phys supporting
+ *		the MIPI_CPHY phy mode.
  * @dp:		Configuration set applicable for phys supporting
  *		the DisplayPort protocol.
  * @lvds:	Configuration set applicable for phys supporting
@@ -78,6 +82,7 @@ union phy_notify {
  */
 union phy_configure_opts {
 	struct phy_configure_opts_mipi_dphy	mipi_dphy;
+	struct phy_configure_opts_mipi_cphy	mipi_cphy;
 	struct phy_configure_opts_dp		dp;
 	struct phy_configure_opts_lvds		lvds;
 	struct phy_configure_opts_hdmi		hdmi;

-- 
2.53.0

[PATCH v3 2/6] phy: Add MIPI C-PHY configuration helpers

[George Neacsu via B4 Relay]

From: George Neacsu <geocausa@gmail.com>

A CSI-2 receiver knows the link frequency of its transmitter, and by the
V4L2 convention a C-PHY link frequency is half the symbol rate on each
trio. Add helpers so that the receiver and the PHY do not each open-code
that conversion, as phy_mipi_dphy_get_default_config_for_hsclk() does
for D-PHY:

- phy_mipi_cphy_get_default_config_for_link_freq() fills a
  configuration from a link frequency and a trio count;
- phy_mipi_cphy_config_validate() checks for a symbol rate and one to
  three trios;
- phy_mipi_cphy_link_freq() gives the link frequency of a configuration.

They are small enough to be inline, so no new Kconfig symbol is needed.

Suggested-by: Bryan O'Donoghue <bod@kernel.org>
Suggested-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: George Neacsu <geocausa@gmail.com>
---
 include/linux/phy/phy-mipi-cphy.h | 60 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/include/linux/phy/phy-mipi-cphy.h b/include/linux/phy/phy-mipi-cphy.h
index 9b748d577b..adc2dcbd2e 100644
--- a/include/linux/phy/phy-mipi-cphy.h
+++ b/include/linux/phy/phy-mipi-cphy.h
@@ -2,8 +2,11 @@
 #ifndef __PHY_MIPI_CPHY_H_
 #define __PHY_MIPI_CPHY_H_
 
+#include <linux/errno.h>
 #include <linux/types.h>
 
+#define PHY_MIPI_CPHY_MAX_TRIOS		3
+
 /**
  * struct phy_configure_opts_mipi_cphy - MIPI C-PHY configuration set
  *
@@ -26,4 +29,61 @@ struct phy_configure_opts_mipi_cphy {
 	u8			trios;
 };
 
+/**
+ * phy_mipi_cphy_config_validate() - Validate a MIPI C-PHY configuration
+ * @cfg: configuration to check
+ *
+ * Return: 0 if @cfg has a symbol rate and one to three trios, -EINVAL
+ * otherwise.
+ */
+static inline int
+phy_mipi_cphy_config_validate(const struct phy_configure_opts_mipi_cphy *cfg)
+{
+	if (!cfg->symbol_rate)
+		return -EINVAL;
+
+	if (cfg->trios < 1 || cfg->trios > PHY_MIPI_CPHY_MAX_TRIOS)
+		return -EINVAL;
+
+	return 0;
+}
+
+/**
+ * phy_mipi_cphy_get_default_config_for_link_freq() - C-PHY configuration
+ * from a link frequency
+ * @link_freq: link frequency in Hz
+ * @trios: number of active trios
+ * @cfg: configuration to fill
+ *
+ * A C-PHY link frequency is half the symbol rate on each trio, the
+ * convention V4L2 uses for the link frequency of a C-PHY transmitter.
+ *
+ * Return: 0 on success, -EINVAL if the resulting configuration is invalid.
+ */
+static inline int
+phy_mipi_cphy_get_default_config_for_link_freq(u64 link_freq,
+					       unsigned int trios,
+					       struct phy_configure_opts_mipi_cphy *cfg)
+{
+	if (trios > PHY_MIPI_CPHY_MAX_TRIOS)
+		return -EINVAL;
+
+	cfg->symbol_rate = link_freq * 2;
+	cfg->trios = trios;
+
+	return phy_mipi_cphy_config_validate(cfg);
+}
+
+/**
+ * phy_mipi_cphy_link_freq() - Link frequency of a MIPI C-PHY configuration
+ * @cfg: configuration
+ *
+ * Return: the link frequency in Hz, half the symbol rate on each trio.
+ */
+static inline u64
+phy_mipi_cphy_link_freq(const struct phy_configure_opts_mipi_cphy *cfg)
+{
+	return cfg->symbol_rate / 2;
+}
+
 #endif /* __PHY_MIPI_CPHY_H_ */

-- 
2.53.0

[PATCH v3 3/6] phy: qcom-mipi-csi2: Rename the D-PHY init sequence

[George Neacsu via B4 Relay]

From: George Neacsu <geocausa@gmail.com>

The init sequence and its size describe the D-PHY mode only. Call them
dphy_init_seq and dphy_lane_array_size, so that a C-PHY sequence can sit
next to them under matching names.

No functional change.

Suggested-by: Bryan O'Donoghue <bod@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: George Neacsu <geocausa@gmail.com>
---
 drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 8 ++++----
 drivers/phy/qualcomm/phy-qcom-mipi-csi2.h          | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
index 966d79c98f..b2d4ec3e81 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
@@ -246,8 +246,8 @@ phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy,
 				     u8 settle_cnt)
 {
 	const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
-	const struct mipi_csi2phy_lane_regs *r = regs->init_seq;
-	int i, array_size = regs->lane_array_size;
+	const struct mipi_csi2phy_lane_regs *r = regs->dphy_init_seq;
+	int i, array_size = regs->dphy_lane_array_size;
 	u32 val;
 
 	for (i = 0; i < array_size; i++, r++) {
@@ -372,8 +372,8 @@ static struct mipi_csi2_genpd x1e_genpds[] = {
 const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = {
 	.ops = &phy_qcom_mipi_csi2_ops_3ph_1_0,
 	.reg_info = {
-		.init_seq = lane_regs_x1e80100,
-		.lane_array_size = ARRAY_SIZE(lane_regs_x1e80100),
+		.dphy_init_seq = lane_regs_x1e80100,
+		.dphy_lane_array_size = ARRAY_SIZE(lane_regs_x1e80100),
 		.common_regs_offset = 0x1000,
 	},
 	.supply_names = (const char **)x1e_supplies,
diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
index 7e55ae0073..0d6031a4d8 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
@@ -48,8 +48,8 @@ struct mipi_csi2phy_lane_regs {
 };
 
 struct mipi_csi2phy_device_regs {
-	const struct mipi_csi2phy_lane_regs *init_seq;
-	const int lane_array_size;
+	const struct mipi_csi2phy_lane_regs *dphy_init_seq;
+	const int dphy_lane_array_size;
 	const u32 common_regs_offset;
 };
 

-- 
2.53.0

[PATCH v3 4/6] phy: qcom-mipi-csi2: Add lane mask and lane polarity helpers

[George Neacsu via B4 Relay]

From: George Neacsu <geocausa@gmail.com>

Move the CTRL5 lane mask and the CTRL9 lane polarity writes out of
phy_qcom_mipi_csi2_lanes_enable() into two helpers,
phy_qcom_mipi_csi2_lane_mask() and
phy_qcom_mipi_csi2_dphy_lane_polarities(). A C-PHY path needs a
different lane mask and no polarities, and with the helpers it can be
added without a goto or a second copy of the common setup.

No functional change.

Suggested-by: Bryan O'Donoghue <bod@kernel.org>
Suggested-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: George Neacsu <geocausa@gmail.com>
---
 drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 64 ++++++++++++++--------
 1 file changed, 42 insertions(+), 22 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
index b2d4ec3e81..a44e104301 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
@@ -268,34 +268,32 @@ phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy,
 	}
 }
 
-static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy,
-					   struct mipi_csi2phy_stream_cfg *cfg)
+/*
+ * CSI_COMMON_CTRL5 is a physical lane power-up bitmap:
+ * - Bits [0,2,4,6] → D-PHY data lanes(LN0, LN2, LN4, LN6)
+ * - Bits [1,3,5] → C-PHY trio lanes(LN1, LN3, LN5)
+ * - Bit [7] → D-PHY clock lane(LNCK) dedicated clock enable
+ */
+static u8 phy_qcom_mipi_csi2_lane_mask(struct mipi_csi2phy_device *csi2phy,
+				       struct mipi_csi2phy_stream_cfg *cfg)
 {
-	const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
 	struct mipi_csi2phy_lanes_cfg *lane_cfg = &cfg->lane_cfg;
-	u8 settle_cnt;
-	u8 val;
+	u8 lane_mask;
 	int i;
 
-	if (cfg->link_freq <= 0)
-		return -EINVAL;
-
-	settle_cnt = phy_qcom_mipi_csi2_settle_cnt_calc(cfg->link_freq, csi2phy->timer_clk_rate);
-	if (!settle_cnt)
-		return -ENODEV;
-
-	/*
-	 * CSI_COMMON_CTRL5 is a physical lane power-up bitmap:
-	 * - Bits [0,2,4,6] → D-PHY data lanes(LN0, LN2, LN4, LN6)
-	 * - Bits [1,3,5] → C-PHY trio lanes(LN1, LN3, LN5)
-	 * - Bit [7] → D-PHY clock lane(LNCK) dedicated clock enable
-	 */
-	val = BIT(lane_cfg->clk.pos);
+	lane_mask = BIT(lane_cfg->clk.pos);
 	for (i = 0; i < cfg->num_data_lanes; i++)
-		val |= BIT(lane_cfg->data[i].pos * 2);
+		lane_mask |= BIT(lane_cfg->data[i].pos * 2);
 
-	writel(val, csi2phy->base +
-	       CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 5));
+	return lane_mask;
+}
+
+static void
+phy_qcom_mipi_csi2_dphy_lane_polarities(struct mipi_csi2phy_device *csi2phy,
+					struct mipi_csi2phy_stream_cfg *cfg)
+{
+	struct mipi_csi2phy_lanes_cfg *lane_cfg = &cfg->lane_cfg;
+	int i;
 
 	/* Lane configuration for polarity @ CSIPHY-base + CTRL9 */
 	for (i = 0; i < cfg->num_data_lanes; i++) {
@@ -308,6 +306,28 @@ static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy,
 
 	if (lane_cfg->clk.pol)
 		writel(BIT(2), csi2phy->base + CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(lane_cfg->clk.pos));
+}
+
+static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy,
+					   struct mipi_csi2phy_stream_cfg *cfg)
+{
+	const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
+	u8 settle_cnt;
+	u8 val;
+	int i;
+
+	if (cfg->link_freq <= 0)
+		return -EINVAL;
+
+	settle_cnt = phy_qcom_mipi_csi2_settle_cnt_calc(cfg->link_freq, csi2phy->timer_clk_rate);
+	if (!settle_cnt)
+		return -ENODEV;
+
+	val = phy_qcom_mipi_csi2_lane_mask(csi2phy, cfg);
+	writel(val, csi2phy->base +
+	       CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 5));
+
+	phy_qcom_mipi_csi2_dphy_lane_polarities(csi2phy, cfg);
 
 	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
 	writel(val, csi2phy->base +

-- 
2.53.0

[PATCH v3 5/6] phy: qcom-mipi-csi2: Use fsleep() for init sequence delays

[George Neacsu via B4 Relay]

From: George Neacsu <geocausa@gmail.com>

The init sequence delays are applied with udelay(), which busy-waits.
That is fine for the 1 us delays in the current D-PHY sequence, but the
X1E80100 C-PHY sequence added next waits about 3 ms after its reset
exit, and busy-waiting that long is wasteful. The sequence is written
from phy_power_on(), in process context, where sleeping is allowed; the
PHY reset just before it already uses usleep_range().

Switch to fsleep(). It still uses udelay() for delays of 10 us or less,
so the existing D-PHY sequence behaves as before.

Suggested-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: George Neacsu <geocausa@gmail.com>
---
 drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
index a44e104301..84c45f67fd 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
@@ -264,7 +264,7 @@ phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy,
 		}
 		writel(val, csi2phy->base + r->reg_addr);
 		if (r->delay_us)
-			udelay(r->delay_us);
+			fsleep(r->delay_us);
 	}
 }
 

-- 
2.53.0

[PATCH v3 6/6] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100

[George Neacsu via B4 Relay]

From: George Neacsu <geocausa@gmail.com>

The CSI2 PHY schema already allows bus-type C-PHY, but the driver
rejects it. Accept it on SoCs that provide a C-PHY sequence, with up to
three trios and no lane polarities. The endpoint's bus-type now sets the
PHY mode, set_mode() only accepts that mode, and in C-PHY mode
configure() takes the symbol rate and keeps the matching link frequency,
so clock scaling works as for D-PHY.

In C-PHY mode, lanes_enable() powers up the trios on the odd CTRL5 bits,
skips the D-PHY lane polarities and writes the C-PHY sequence. The
settle count is computed as for D-PHY: with a C-PHY link frequency of
half the symbol rate, the unit interval in the existing formula is one
symbol, which is also how David Heidelberg's CAMSS C-PHY series
computes it.

The X1E80100 sequence is Qualcomm's for the v2.1.2 3PH PHY at 2.5 Gsps,
taken from the downstream camera driver's GPL-2.0
cam_csiphy_2_1_2_hwreg.h (csiphy_3ph_v2_1_2_reg, datarate_212_2p5Gsps
and the 3PH reset exit), as the D-PHY sequence above it is. Its three
settle count entries are the ones downstream marks as such. The trios
sit in lane slots 1, 3 and 5, so the per-trio registers are written
with a CSIPHY_LN_CTRLn() address macro.

Tested on the Surface Pro 11 (X1E80100), booting next-20261015 with
this series, David Heidelberg's CAMSS C-PHY series v9 and two CAMSS
patches on top: the IMX681 on CSIPHY2, one trio at 2.4 Gsym/s, streams
3844x2640 at 30 fps through CSID1 and an RDI, and its colour bars are
byte-identical to the same pattern captured with an out-of-tree driver.
The timer runs at 400 MHz and the computed settle count is 28. D-PHY is
unchanged: an OV13858 on CSIPHY1 over four lanes streams at 29.9 fps.

Assisted-by: Claude:claude-opus-5-5
Signed-off-by: George Neacsu <geocausa@gmail.com>
---
 drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 168 ++++++++++++++++++++-
 drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c     |  53 ++++++-
 drivers/phy/qualcomm/phy-qcom-mipi-csi2.h          |   2 +
 3 files changed, 212 insertions(+), 11 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
index 84c45f67fd..f09ef9b41c 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
@@ -22,6 +22,7 @@
 #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n)	((offset) + 0xb0 + 0x4 * (n))
 
 #define CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(n)		((0x200 * (n)) + 0x24)
+#define CSIPHY_LN_CTRLn(ln, n)			((0x200 * (ln)) + 0x4 * (n))
 
 /*
  * 3 phase CSI has 19 common status regs with only 0-10 being used
@@ -161,6 +162,144 @@ mipi_csi2phy_lane_regs lane_regs_x1e80100[] = {
 	{.reg_addr = 0x0c64, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL},
 };
 
+/* Qualcomm's 2.5 Gsps settings, from the GPL-2.0 cam_csiphy_2_1_2_hwreg.h */
+static const struct
+mipi_csi2phy_lane_regs lane_regs_v2_1_2_cphy[] = {
+	/* Power up lanes 3ph mode */
+	{.reg_addr = 0x101c, .reg_data = 0x7a, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x1018, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	/* datarate_212_2p5Gsps: AFE settings */
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 26), .reg_data = 0xf1, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 37), .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 34), .reg_data = 0x20, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 30), .reg_data = 0x20, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 27), .reg_data = 0x3d, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 35), .reg_data = 0x30, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 28), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 29), .reg_data = 0x03, .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 26), .reg_data = 0xf1, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 37), .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 34), .reg_data = 0x20, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 30), .reg_data = 0x20, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 27), .reg_data = 0x3d, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 35), .reg_data = 0x30, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 28), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 29), .reg_data = 0x03, .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 26), .reg_data = 0xf1, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 37), .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 34), .reg_data = 0x20, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 30), .reg_data = 0x20, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 27), .reg_data = 0x3d, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 35), .reg_data = 0x30, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 28), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 29), .reg_data = 0x03, .delay_us = 10,
+	 .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	/* csiphy_3ph_v2_1_2_reg */
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 61), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 62), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 63), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 60), .reg_data = 0xef, .delay_us = 3,
+	 .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 61), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 62), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 63), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 60), .reg_data = 0xef, .delay_us = 3,
+	 .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 61), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 62), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 63), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 60), .reg_data = 0xef, .delay_us = 3,
+	 .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	/* datarate_212_2p5Gsps, then csiphy_3ph_v2_1_2_reg */
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 3), .reg_data = 0x22,
+	 .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 2), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 4), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 5), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 1), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 57), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 58), .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 59), .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 6), .reg_data = 0x3e, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 7), .reg_data = 0x41, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 8), .reg_data = 0x41, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 9), .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 10), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 11), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 25), .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 17), .reg_data = 0xb2, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 68), .reg_data = 0x35, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 47), .reg_data = 0xd0, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 21), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 16), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 24), .reg_data = 0xa8, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 33), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(1, 36), .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	/* datarate_212_2p5Gsps, then csiphy_3ph_v2_1_2_reg */
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 3), .reg_data = 0x22,
+	 .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 2), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 4), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 5), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 1), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 57), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 58), .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 59), .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 6), .reg_data = 0x3e, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 7), .reg_data = 0x41, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 8), .reg_data = 0x41, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 9), .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 10), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 11), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 25), .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 17), .reg_data = 0xb2, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 68), .reg_data = 0x35, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 47), .reg_data = 0xd0, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 21), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 16), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 24), .reg_data = 0xa8, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 33), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(3, 36), .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	/* datarate_212_2p5Gsps, then csiphy_3ph_v2_1_2_reg */
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 3), .reg_data = 0x22,
+	 .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 2), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 4), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 5), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 1), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 57), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 58), .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 59), .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 6), .reg_data = 0x3e, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 7), .reg_data = 0x41, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 8), .reg_data = 0x41, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 9), .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 10), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 11), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 25), .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 17), .reg_data = 0xb2, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 68), .reg_data = 0x35, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 47), .reg_data = 0xd0, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 21), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 16), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 24), .reg_data = 0xa8, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 33), .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = CSIPHY_LN_CTRLn(5, 36), .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS},
+
+	/* csiphy_reset_exit_reg_2_1_2, 3PH */
+	{.reg_addr = 0x1000, .reg_data = 0x0e, .delay_us = 3048,
+	 .param_type = CSIPHY_DEFAULT_PARAMS},
+};
+
 static inline const struct mipi_csi2phy_device_regs *
 csi2phy_dev_to_regs(struct mipi_csi2phy_device *csi2phy)
 {
@@ -246,9 +385,18 @@ phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy,
 				     u8 settle_cnt)
 {
 	const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
-	const struct mipi_csi2phy_lane_regs *r = regs->dphy_init_seq;
-	int i, array_size = regs->dphy_lane_array_size;
+	const struct mipi_csi2phy_lane_regs *r;
+	int array_size;
 	u32 val;
+	int i;
+
+	if (csi2phy->phy_mode == PHY_MODE_MIPI_CPHY) {
+		r = regs->cphy_init_seq;
+		array_size = regs->cphy_lane_array_size;
+	} else {
+		r = regs->dphy_init_seq;
+		array_size = regs->dphy_lane_array_size;
+	}
 
 	for (i = 0; i < array_size; i++, r++) {
 		switch (r->param_type) {
@@ -278,12 +426,17 @@ static u8 phy_qcom_mipi_csi2_lane_mask(struct mipi_csi2phy_device *csi2phy,
 				       struct mipi_csi2phy_stream_cfg *cfg)
 {
 	struct mipi_csi2phy_lanes_cfg *lane_cfg = &cfg->lane_cfg;
-	u8 lane_mask;
+	u8 lane_mask = 0;
+	u8 offset = 0;
 	int i;
 
-	lane_mask = BIT(lane_cfg->clk.pos);
+	if (csi2phy->phy_mode == PHY_MODE_MIPI_CPHY)
+		offset = 1;
+	else
+		lane_mask = BIT(lane_cfg->clk.pos);
+
 	for (i = 0; i < cfg->num_data_lanes; i++)
-		lane_mask |= BIT(lane_cfg->data[i].pos * 2);
+		lane_mask |= BIT(lane_cfg->data[i].pos * 2 + offset);
 
 	return lane_mask;
 }
@@ -327,7 +480,8 @@ static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy,
 	writel(val, csi2phy->base +
 	       CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 5));
 
-	phy_qcom_mipi_csi2_dphy_lane_polarities(csi2phy, cfg);
+	if (csi2phy->phy_mode == PHY_MODE_MIPI_DPHY)
+		phy_qcom_mipi_csi2_dphy_lane_polarities(csi2phy, cfg);
 
 	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
 	writel(val, csi2phy->base +
@@ -394,6 +548,8 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = {
 	.reg_info = {
 		.dphy_init_seq = lane_regs_x1e80100,
 		.dphy_lane_array_size = ARRAY_SIZE(lane_regs_x1e80100),
+		.cphy_init_seq = lane_regs_v2_1_2_cphy,
+		.cphy_lane_array_size = ARRAY_SIZE(lane_regs_v2_1_2_cphy),
 		.common_regs_offset = 0x1000,
 	},
 	.supply_names = (const char **)x1e_supplies,
diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
index c0a4fa20ea..1185561a1e 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
@@ -96,6 +96,25 @@ phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy,
 	return ret;
 }
 
+static int
+phy_qcom_mipi_csi2_configure_cphy(struct mipi_csi2phy_device *csi2phy,
+				  struct phy_configure_opts_mipi_cphy *cphy_cfg)
+{
+	struct mipi_csi2phy_stream_cfg *stream_cfg = &csi2phy->stream_cfg;
+	int ret;
+
+	ret = phy_mipi_cphy_config_validate(cphy_cfg);
+	if (ret)
+		return ret;
+
+	if (cphy_cfg->trios != stream_cfg->num_data_lanes)
+		return -EINVAL;
+
+	stream_cfg->link_freq = phy_mipi_cphy_link_freq(cphy_cfg);
+
+	return 0;
+}
+
 static int phy_qcom_mipi_csi2_configure(struct phy *phy,
 					union phy_configure_opts *opts)
 {
@@ -104,6 +123,9 @@ static int phy_qcom_mipi_csi2_configure(struct phy *phy,
 	struct mipi_csi2phy_stream_cfg *stream_cfg = &csi2phy->stream_cfg;
 	int ret;
 
+	if (csi2phy->phy_mode == PHY_MODE_MIPI_CPHY)
+		return phy_qcom_mipi_csi2_configure_cphy(csi2phy, &opts->mipi_cphy);
+
 	ret = phy_mipi_dphy_config_validate(dphy_cfg);
 	if (ret)
 		return ret;
@@ -124,10 +146,13 @@ static int phy_qcom_mipi_csi2_set_mode(struct phy *phy,
 {
 	struct mipi_csi2phy_device *csi2phy = phy_get_drvdata(phy);
 
-	if (mode != PHY_MODE_MIPI_DPHY)
+	if (mode != PHY_MODE_MIPI_DPHY && mode != PHY_MODE_MIPI_CPHY)
 		return -EOPNOTSUPP;
 
-	csi2phy->phy_mode = mode;
+	/* The endpoint's bus-type sets the mode; only that one is accepted. */
+	if (mode != csi2phy->phy_mode)
+		return -EINVAL;
+
 	return 0;
 }
 
@@ -258,6 +283,7 @@ static int phy_qcom_mipi_csi2_parse_routing(struct mipi_csi2phy_device *csi2phy)
 	struct fwnode_handle *ep;
 	int num_polarities;
 	int num_data_lanes;
+	int max_lanes;
 	u32 bus_type;
 	int i, ret;
 
@@ -278,14 +304,26 @@ static int phy_qcom_mipi_csi2_parse_routing(struct mipi_csi2phy_device *csi2phy)
 	bus_type = MEDIA_BUS_TYPE_CSI2_DPHY;
 	fwnode_property_read_u32(ep, "bus-type", &bus_type);
 
-	if (bus_type != MEDIA_BUS_TYPE_CSI2_DPHY) {
+	switch (bus_type) {
+	case MEDIA_BUS_TYPE_CSI2_DPHY:
+		csi2phy->phy_mode = PHY_MODE_MIPI_DPHY;
+		max_lanes = CSI2_MAX_DATA_LANES;
+		break;
+	case MEDIA_BUS_TYPE_CSI2_CPHY:
+		if (csi2phy->soc_cfg->reg_info.cphy_init_seq) {
+			csi2phy->phy_mode = PHY_MODE_MIPI_CPHY;
+			max_lanes = PHY_MIPI_CPHY_MAX_TRIOS;
+			break;
+		}
+		fallthrough;
+	default:
 		ret = -EOPNOTSUPP;
 		dev_err(dev, "Unsupported bus-type %u\n", bus_type);
 		goto out_put;
 	}
 
 	num_data_lanes = fwnode_property_count_u32(ep, "data-lanes");
-	if (num_data_lanes < 1 || num_data_lanes > CSI2_MAX_DATA_LANES) {
+	if (num_data_lanes < 1 || num_data_lanes > max_lanes) {
 		ret = -EINVAL;
 		dev_err(dev, "Invalid data-lanes count: %d\n", num_data_lanes);
 		goto out_put;
@@ -302,6 +340,11 @@ static int phy_qcom_mipi_csi2_parse_routing(struct mipi_csi2phy_device *csi2phy)
 	/* lane-polarities: optional, up to num_data_lanes + 1 entries */
 	memset(lane_polarities, 0x00, sizeof(lane_polarities));
 	num_polarities = fwnode_property_count_u32(ep, "lane-polarities");
+	if (num_polarities > 0 && bus_type == MEDIA_BUS_TYPE_CSI2_CPHY) {
+		ret = -EINVAL;
+		dev_err(dev, "lane-polarities do not apply to C-PHY\n");
+		goto out_put;
+	}
 	if (num_polarities > 0) {
 		if (num_polarities != stream_cfg->num_data_lanes + 1) {
 			ret = -EINVAL;
@@ -322,7 +365,7 @@ static int phy_qcom_mipi_csi2_parse_routing(struct mipi_csi2phy_device *csi2phy)
 	csi2phy->stream_cfg.lane_cfg.clk.pol = lane_polarities[0];
 
 	for (i = 0; i < csi2phy->stream_cfg.num_data_lanes; i++) {
-		if (data_lanes[i] < 1 || data_lanes[i] > CSI2_MAX_DATA_LANES) {
+		if (data_lanes[i] < 1 || data_lanes[i] > max_lanes) {
 			dev_err(dev, "Invalid lane %d\n", data_lanes[i]);
 			ret = -EINVAL;
 			goto out_put;
diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
index 0d6031a4d8..f49f334fd5 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
@@ -50,6 +50,8 @@ struct mipi_csi2phy_lane_regs {
 struct mipi_csi2phy_device_regs {
 	const struct mipi_csi2phy_lane_regs *dphy_init_seq;
 	const int dphy_lane_array_size;
+	const struct mipi_csi2phy_lane_regs *cphy_init_seq;
+	const int cphy_lane_array_size;
 	const u32 common_regs_offset;
 };
 

-- 
2.53.0

Re: [PATCH v3 6/6] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100

[David Heidelberg]

On 16/10/2026 16:56, George Neacsu via B4 Relay wrote:
> From: George Neacsu <geocausa@gmail.com>
> 
> The CSI2 PHY schema already allows bus-type C-PHY, but the driver
> rejects it. Accept it on SoCs that provide a C-PHY sequence, with up to
> three trios and no lane polarities. The endpoint's bus-type now sets the
> PHY mode, set_mode() only accepts that mode, and in C-PHY mode
> configure() takes the symbol rate and keeps the matching link frequency,
> so clock scaling works as for D-PHY.
> 
> In C-PHY mode, lanes_enable() powers up the trios on the odd CTRL5 bits,
> skips the D-PHY lane polarities and writes the C-PHY sequence. The
> settle count is computed as for D-PHY: with a C-PHY link frequency of
> half the symbol rate, the unit interval in the existing formula is one
> symbol, which is also how David Heidelberg's CAMSS C-PHY series
> computes it.
> 
> The X1E80100 sequence is Qualcomm's for the v2.1.2 3PH PHY at 2.5 Gsps,
> taken from the downstream camera driver's GPL-2.0
> cam_csiphy_2_1_2_hwreg.h (csiphy_3ph_v2_1_2_reg, datarate_212_2p5Gsps
> and the 3PH reset exit), as the D-PHY sequence above it is. Its three
> settle count entries are the ones downstream marks as such. The trios
> sit in lane slots 1, 3 and 5, so the per-trio registers are written
> with a CSIPHY_LN_CTRLn() address macro.
> 
> Tested on the Surface Pro 11 (X1E80100), booting next-20261015 with
> this series, David Heidelberg's CAMSS C-PHY series v9 and two CAMSS
> patches on top: the IMX681 on CSIPHY2, one trio at 2.4 Gsym/s, streams
> 3844x2640 at 30 fps through CSID1 and an RDI, and its colour bars are
> byte-identical to the same pattern captured with an out-of-tree driver.
> The timer runs at 400 MHz and the computed settle count is 28. D-PHY is
> unchanged: an OV13858 on CSIPHY1 over four lanes streams at 29.9 fps.
> 
> Assisted-by: Claude:claude-opus-5-5
> Signed-off-by: George Neacsu <geocausa@gmail.com>
> ---
>   drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 168 ++++++++++++++++++++-
>   drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c     |  53 ++++++-
>   drivers/phy/qualcomm/phy-qcom-mipi-csi2.h          |   2 +
>   3 files changed, 212 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
> index 84c45f67fd..f09ef9b41c 100644
> --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
> +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
> @@ -22,6 +22,7 @@
>   #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n)	((offset) + 0xb0 + 0x4 * (n))
>   
>   #define CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(n)		((0x200 * (n)) + 0x24)
> +#define CSIPHY_LN_CTRLn(ln, n)			((0x200 * (ln)) + 0x4 * (n))
>   
>   /*
>    * 3 phase CSI has 19 common status regs with only 0-10 being used
> @@ -161,6 +162,144 @@ mipi_csi2phy_lane_regs lane_regs_x1e80100[] = {
>   	{.reg_addr = 0x0c64, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL},
>   };
>   
> +/* Qualcomm's 2.5 Gsps settings, from the GPL-2.0 cam_csiphy_2_1_2_hwreg.h */
> +static const struct
> +mipi_csi2phy_lane_regs lane_regs_v2_1_2_cphy[] = {
> +	/* Power up lanes 3ph mode */
> +	{.reg_addr = 0x101c, .reg_data = 0x7a, .param_type = CSIPHY_DEFAULT_PARAMS},
> +	{.reg_addr = 0x1018, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> +
> +	/* datarate_212_2p5Gsps: AFE settings */
> +	{.reg_addr = CSIPHY_LN_CTRLn(1, 26), .reg_data = 0xf1, .param_type = CSIPHY_DEFAULT_PARAMS},

Thank you for the change. While the lane being decimal number is completely 
fine, I believe the register passed should stay in hex :)

Otherwise LGTM.

David

[...]

[...]

Re: [PATCH v3 6/6] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100

[George Neacsu]

Hi David,

On 16/10/2026 16:10, David Heidelberg wrote:
>> +	{.reg_addr = CSIPHY_LN_CTRLn(1, 26), .reg_data = 0xf1, .param_type = CSIPHY_DEFAULT_PARAMS},
>
> Thank you for the change. While the lane being decimal number is completely
> fine, I believe the register passed should stay in hex :)

Agreed. In the next version the macro will take the register offset
within the lane in hex, e.g. CSIPHY_LN_REG(1, 0x68), so each entry
reads like the downstream header. The object code stays the same.

Thanks,
George

Re: [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY for X1E80100

[Bryan O'Donoghue]

On 16/10/2026 15:56, George Neacsu via B4 Relay wrote:
> The series is on next-20261015 and applies there on its own. The two
> CAMSS patches that use it build on David's "media: camss: Add support
> for C-PHY configuration on Qualcomm platforms" v9, which is not in
> linux-next yet, so I will send them on top of David's series:
> https://lore.kernel.org/all/20260729-qcom-cphy-v9-0-1f8d9fdab037@ixit.cz/

This part confuses me.

Using drivers/phy means not doing CPHY inline in CAMSS. If you require 
patches from the V9 series - you should cherry-pick them - sign off them 
and the post them.

---
bod

Re: [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY for X1E80100

[George Neacsu]

Hi Bryan,

On 16/10/2026 17:09, Bryan O'Donoghue wrote:
> Using drivers/phy means not doing CPHY inline in CAMSS. If you require
> patches from the V9 series - you should cherry-pick them - sign off them
> and the post them.

Understood. The two CAMSS patches need only three of David's nine
patches, and none of his CSIPHY C-PHY tables:

- 2/9, which keeps the endpoint's bus type in the lane configuration;
- 4/9, which adds the CSID PHY select for C-PHY;
- 8/9, which lets camss_get_link_freq() account for C-PHY symbols.

The other six program C-PHY inline in camss-csiphy-3ph-1-0.c, which the
PHY API path does not use.

So the CAMSS side will go out as one series on top of this one: those
three, kept under David's authorship with my sign-off added, followed
by the two CAMSS patches. David, is that all right with you?

Thanks,
George

Re: [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY for X1E80100

[David Heidelberg]

On 16/10/2026 23:48, George Neacsu wrote:
> Hi Bryan,
> 
> On 16/10/2026 17:09, Bryan O'Donoghue wrote:
>> Using drivers/phy means not doing CPHY inline in CAMSS. If you require
>> patches from the V9 series - you should cherry-pick them - sign off them
>> and the post them.
> 
> Understood. The two CAMSS patches need only three of David's nine
> patches, and none of his CSIPHY C-PHY tables:
> 
> - 2/9, which keeps the endpoint's bus type in the lane configuration;
> - 4/9, which adds the CSID PHY select for C-PHY;
> - 8/9, which lets camss_get_link_freq() account for C-PHY symbols.
> 
> The other six program C-PHY inline in camss-csiphy-3ph-1-0.c, which the
> PHY API path does not use.
> 
> So the CAMSS side will go out as one series on top of this one: those
> three, kept under David's authorship with my sign-off added, followed
> by the two CAMSS patches. David, is that all right with you?

Yes, sure. Just 'git commit --amend --sign' :)

I didn't expected these patches will get in (due to PHY rework), so if they do 
I'll be happy, because I can drop them from sdm845 tree later.

David

> 
> Thanks,
> George