Re: [PATCH v4 10/15] drm/msm: Switch to generic PAS TZ APIs

[Sumit Garg <sumit.garg@kernel.org>]

On Wed, Apr 29, 2026 at 07:29:54PM +0530, Mukesh Ojha wrote:
> On Mon, Apr 27, 2026 at 03:25:58PM +0530, Sumit Garg wrote:
> > From: Sumit Garg <sumit.garg@oss.qualcomm.com>
> > 
> > Switch drm/msm client drivers over to generic PAS TZ APIs. Generic PAS
> > TZ service allows to support multiple TZ implementation backends like QTEE
> > based SCM PAS service, OP-TEE based PAS service and any further future TZ
> > backend service.
> > 
> > Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> > ---
> >  drivers/gpu/drm/msm/Kconfig             |  1 +
> >  drivers/gpu/drm/msm/adreno/a5xx_gpu.c   |  4 ++--
> >  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 ++++++-----
> >  3 files changed, 9 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gdrivers/gpu/drm/msm/Kconfigpu/drm/msm/Kconfig
> > index 250246f81ea9..09469d56513b 100644
> > --- a/drivers/gpu/drm/msm/Kconfig
> > +++ b/drivers/gpu/drm/msm/Kconfig
> > @@ -21,6 +21,7 @@ config DRM_MSM
> >  	select SHMEM
> >  	select TMPFS
> >  	select QCOM_SCM
> 
> do we need this ?

Yeah we do..

> 
> > +	select QCOM_PAS
> >  	select QCOM_UBWC_CONFIG
> >  	select WANT_DEV_COREDUMP
> >  	select SND_SOC_HDMI_CODEC if SND_SOC
> > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > index 79acae11154a..b556da823897 100644
> > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > @@ -5,7 +5,7 @@
> >  #include <linux/kernel.h>
> >  #include <linux/types.h>
> >  #include <linux/cpumask.h>
> > -#include <linux/firmware/qcom/qcom_scm.h>
> > +#include <linux/firmware/qcom/qcom_pas.h>
> >  #include <linux/pm_opp.h>
> >  #include <linux/nvmem-consumer.h>
> >  #include <linux/slab.h>
> > @@ -653,7 +653,7 @@ static int a5xx_zap_shader_resume(struct msm_gpu *gpu)
> >  	if (adreno_is_a506(adreno_gpu))
> >  		return 0;
> >  
> > -	ret = qcom_scm_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID);
> > +	ret = qcom_pas_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID);
> >  	if (ret)
> >  		DRM_ERROR("%s: zap-shader resume failed: %d\n",
> >  			gpu->name, ret);
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > index 66f80f2d12f9..6d68edf0578c 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > @@ -8,6 +8,7 @@
> >  
> >  #include <linux/ascii85.h>
> >  #include <linux/interconnect.h>
> > +#include <linux/firmware/qcom/qcom_pas.h>
> >  #include <linux/firmware/qcom/qcom_scm.h>
> 
> do we need this ?
> 

..needed for qcom_scm_set_gpu_smmu_aperture() API.

> >  #include <linux/kernel.h>
> >  #include <linux/of_reserved_mem.h>
> > @@ -146,10 +147,10 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
> >  		goto out;
> >  
> >  	/* Send the image to the secure world */
> > -	ret = qcom_scm_pas_auth_and_reset(pasid);
> > +	ret = qcom_pas_auth_and_reset(pasid);
> >  
> >  	/*
> > -	 * If the scm call returns -EOPNOTSUPP we assume that this target
> > +	 * If the pas call returns -EOPNOTSUPP we assume that this target
> >  	 * doesn't need/support the zap shader so quietly fail
> >  	 */
> >  	if (ret == -EOPNOTSUPP)
> > @@ -175,9 +176,9 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
> >  	if (!zap_available)
> >  		return -ENODEV;
> >  
> > -	/* We need SCM to be able to load the firmware */
> > -	if (!qcom_scm_is_available()) {
> > -		DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
> > +	/* We need PAS to be able to load the firmware */
> > +	if (!qcom_pas_is_available()) {
> > +		DRM_DEV_ERROR(&pdev->dev, "Qcom PAS is not available\n");
> >  		return -EPROBE_DEFER;
> >  	}
> >  
> > -- 
> > 2.51.0
> > 
> 
> Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> 
> 

Thanks.

-Sumit