From: "SkyLake Huang (黃啟澤)" <SkyLake.Huang@mediatek.com>
To: "andrew@lunn.ch" <andrew@lunn.ch>
Cc: "dqfext@gmail.com" <dqfext@gmail.com>,
"Steven Liu (劉人豪)" <steven.liu@mediatek.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"edumazet@google.com" <edumazet@google.com>,
"linux@armlinux.org.uk" <linux@armlinux.org.uk>,
"hkallweit1@gmail.com" <hkallweit1@gmail.com>,
"horms@kernel.org" <horms@kernel.org>,
"daniel@makrotopia.org" <daniel@makrotopia.org>,
"pabeni@redhat.com" <pabeni@redhat.com>,
"kuba@kernel.org" <kuba@kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>
Subject: Re: [PATCH net-next v2 3/3] net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on MT7988
Date: Tue, 13 May 2025 10:55:57 +0000 [thread overview]
Message-ID: <062fff7f65bb9654922be4cac34e3c6fe01d7029.camel@mediatek.com> (raw)
In-Reply-To: <724eff11-c6d1-40e1-a99f-205f5426a07d@lunn.ch>
On Wed, 2025-02-19 at 16:47 +0100, Andrew Lunn wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> > +config MEDIATEK_2P5GE_PHY
> > + tristate "MediaTek 2.5Gb Ethernet PHYs"
> > + depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
> > + select MTK_NET_PHYLIB
> > + help
> > + Supports MediaTek SoC built-in 2.5Gb Ethernet PHYs.
> > +
> > + This will load necessary firmware and add appropriate time
> > delay.
> > + Accelerate this procedure through internal pbus instead of
> > MDIO
> > + bus. Certain link-up issues will also be fixed here.
>
> Please keep the file sorted, this should be the first entry.
>
I'll sort in this way in v3:
config MEDIATEK_2P5GE_PHY
...
config MEDIATEK_GE_SOC_PHY
...
config MTK_NET_PHYLIB
...
config MEDIATEK_GE_PHY
...
> > diff --git a/drivers/net/phy/mediatek/Makefile
> > b/drivers/net/phy/mediatek/Makefile
> > index 814879d0abe5..c6db8abd2c9c 100644
> > --- a/drivers/net/phy/mediatek/Makefile
> > +++ b/drivers/net/phy/mediatek/Makefile
> > @@ -2,3 +2,4 @@
> > obj-$(CONFIG_MTK_NET_PHYLIB) += mtk-phy-lib.o
> > obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
> > obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
> > +obj-$(CONFIG_MEDIATEK_2P5GE_PHY) += mtk-2p5ge.o
>
> I suppose you could say this file is sorted in reverse order so is
> correct?
>
I'll change this in v3 in this way:
obj-$(CONFIG_MEDIATEK_2P5GE_PHY) += mtk-2p5ge.o
obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
obj-$(CONFIG_MTK_NET_PHYLIB) += mtk-phy-lib.o
obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
> > diff --git a/drivers/net/phy/mediatek/mtk-2p5ge.c
> > b/drivers/net/phy/mediatek/mtk-2p5ge.c
> > new file mode 100644
> > index 000000000000..adb03df331ab
> > --- /dev/null
> > +++ b/drivers/net/phy/mediatek/mtk-2p5ge.c
> > @@ -0,0 +1,346 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +#include <linux/bitfield.h>
> > +#include <linux/firmware.h>
> > +#include <linux/module.h>
> > +#include <linux/nvmem-consumer.h>
>
> Is this header needed?
>
> > +#include <linux/of_address.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/pinctrl/consumer.h>
> > +#include <linux/phy.h>
> > +#include <linux/pm_domain.h>
> > +#include <linux/pm_runtime.h>
>
> And these two? Please only use those that are needed.
>
I'll remove linux/nvmem-
consumer.h>/<linux/pm_domain.h>/<linux/pm_runtime.h> in v3. I forgot
removing them after developing this driver.
> > +static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
> > +{
> > +
> > + writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG);
> > + writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG);
> > + phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
> > + /* We need a delay here to stabilize initialization of MCU */
> > + usleep_range(7000, 8000);
>
> Does the reset bit clear when the MCU is ready? That is what 802.3
> defines. phy_poll_reset() might do what you need.
CL22 reset bit will be cleared right after I set it on MT7988.
usleep_range() here is used to allow the MCU to stabilize, rather than
to wait for the reset to complete.
>
> > + dev_info(dev, "Firmware loading/trigger ok.\n");
>
> dev_dbg(), if at all. You have already spammed the log with the
> firmware version, so this adds nothing useful.
Well then... In v3, I'll remove this line and print firmware version at
last like this:
for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4)
writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG);
writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG);
phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
/* We need a delay here to stabilize initialization of MCU */
usleep_range(7000, 8000);
dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n",
be16_to_cpu(*((__be16 *)(fw->data +
MT7988_2P5GE_PMB_FW_SIZE - 8))),
*(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6),
*(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5),
*(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2),
*(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1));
priv->fw_loaded = true;
> > + phydev->duplex = DUPLEX_FULL;
> > + /* FIXME:
> > + * The current firmware always enables rate
> > adaptation mode.
> > + */
> > + phydev->rate_matching = RATE_MATCH_PAUSE;
>
> Can we tell current firmware for future firmware? Is this actually
> fixable?
>
We decided to always enable rate adaptation mode for MT7988's current
and future built-in 2.5GbE firmware. I'll remove FIXME comment here in
v3.
> > + }
> > +
> > + return 0;
> > +}
> > +
>
>
>
> > +static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
> > +{
> > + struct mtk_i2p5ge_phy_priv *priv;
> > +
> > + priv = devm_kzalloc(&phydev->mdio.dev,
> > + sizeof(struct mtk_i2p5ge_phy_priv),
> > GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + switch (phydev->drv->phy_id) {
> > + case MTK_2P5GPHY_ID_MT7988:
> > + /* The original hardware only sets MDIO_DEVS_PMAPMD
> > */
>
> What do you mean by "original hardware"?
>
> You use PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988), so do you mean
> revision 0 is broken, but revision 1 fixed it?
>
I'll fix this ambiguous comment to:
/* This built-in 2.5GbE hardware only sets MDIO_DEVS_PMAPMD. Set the *
rest by this driver since PCS/AN/VEND1/VEND2 mmds exist.
*/
>
> > + phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS |
> > + MDIO_DEVS_AN |
> > + MDIO_DEVS_VEND1 |
> > + MDIO_DEVS_VEND2;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + priv->fw_loaded = false;
> > + phydev->priv = priv;
> > +
> > + mtk_phy_leds_state_init(phydev);
>
> The LEDs work without firmware?
>
> Andrew
>
> ---
> pw-bot: cr
I'll remove this line v3 and propose LED part in later patchset.
BRs,
Sky
prev parent reply other threads:[~2025-05-13 12:04 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-19 8:39 [PATCH net-next v2 0/2] Add 2.5G ethernet phy support on MT7988 Sky Huang
2025-02-19 8:39 ` [PATCH net-next v2 1/3] net: phy: mediatek: Add 2.5Gphy firmware dt-bindings and dts node Sky Huang
2025-02-19 12:26 ` Krzysztof Kozlowski
2025-02-19 15:26 ` Andrew Lunn
2025-02-19 15:30 ` Daniel Golle
2025-02-25 10:59 ` SkyLake Huang (黃啟澤)
2025-02-25 13:51 ` Andrew Lunn
2025-02-26 4:14 ` SkyLake Huang (黃啟澤)
2025-02-26 13:26 ` Andrew Lunn
2025-05-13 9:45 ` SkyLake Huang (黃啟澤)
2025-02-19 8:39 ` [PATCH net-next v2 2/3] dts: mt7988a: Add built-in ethernet phy firmware node Sky Huang
2025-02-19 12:28 ` Krzysztof Kozlowski
2025-02-19 8:39 ` [PATCH net-next v2 3/3] net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on MT7988 Sky Huang
2025-02-19 9:33 ` Russell King (Oracle)
2025-02-19 15:16 ` Andrew Lunn
2025-02-26 6:48 ` SkyLake Huang (黃啟澤)
2025-02-26 9:52 ` Russell King (Oracle)
2025-05-13 11:13 ` SkyLake Huang (黃啟澤)
2025-02-26 13:32 ` Andrew Lunn
2025-05-13 11:15 ` SkyLake Huang (黃啟澤)
2025-05-13 10:12 ` SkyLake Huang (黃啟澤)
2025-05-13 11:01 ` SkyLake Huang (黃啟澤)
2025-05-13 12:32 ` Andrew Lunn
2025-02-19 15:47 ` Andrew Lunn
2025-05-13 10:55 ` SkyLake Huang (黃啟澤) [this message]
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