From: Biao Huang <biao.huang@mediatek.com>
To: Jose Abreu <joabreu@synopsys.com>, davem@davemloft.net
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yt.shen@mediatek.com, biao.huang@mediatek.com,
jianguo.zhang@mediatek.com
Subject: [v2, PATCH 2/4] net: stmmac: fix csr_clk can't be zero issue
Date: Tue, 14 May 2019 10:28:51 +0800 [thread overview]
Message-ID: <1557800933-30759-3-git-send-email-biao.huang@mediatek.com> (raw)
In-Reply-To: <1557800933-30759-1-git-send-email-biao.huang@mediatek.com>
The specific clk_csr value can be zero, and
stmmac_clk is necessary for MDC clock which can be set dynamically.
So, change the condition from plat->clk_csr to plat->stmmac_clk to
fix clk_csr can't be zero issue.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +++---
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 ++++-
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 906f2be..a905b63 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -4374,10 +4374,10 @@ int stmmac_dvr_probe(struct device *device,
* set the MDC clock dynamically according to the csr actual
* clock input.
*/
- if (!priv->plat->clk_csr)
- stmmac_clk_csr_set(priv);
- else
+ if (priv->plat->clk_csr >= 0)
priv->clk_csr = priv->plat->clk_csr;
+ else
+ stmmac_clk_csr_set(priv);
stmmac_check_pcs_mode(priv);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 3031f2b..f45bfbe 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -408,7 +408,10 @@ struct plat_stmmacenet_data *
/* Default to phy auto-detection */
plat->phy_addr = -1;
- /* Get clk_csr from device tree */
+ /* Default to get clk_csr from stmmac_clk_crs_set(),
+ * or get clk_csr from device tree.
+ */
+ plat->clk_csr = -1;
of_property_read_u32(np, "clk_csr", &plat->clk_csr);
/* "snps,phy-addr" is not a standard property. Mark it as deprecated
--
1.7.9.5
next prev parent reply other threads:[~2019-05-14 2:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-14 2:28 [v2, PATCH 0/4] fix some bugs in stmmac Biao Huang
2019-05-14 2:28 ` [v2, PATCH 1/4] net: stmmac: update rx tail pointer register to fix rx dma hang issue Biao Huang
2019-05-14 2:28 ` Biao Huang [this message]
2019-05-14 2:28 ` [v2, PATCH 3/4] net: stmmac: write the modified value back to MTL_OPERATION_MODE Biao Huang
2019-05-14 2:28 ` [v2, PATCH 4/4] net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail Biao Huang
2019-05-14 3:00 ` [v2, PATCH 0/4] fix some bugs in stmmac Andrew Lunn
2019-05-14 3:38 ` biao huang
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