From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: Weiyi Lu <weiyi.lu@mediatek.com>,
srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org,
Yingjoe Chen <yingjoe.chen@mediatek.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 23/24] arm64: dts: mediatek: Add mt8192 clock controllers
Date: Mon, 9 Nov 2020 10:03:48 +0800 [thread overview]
Message-ID: <1604887429-29445-24-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1604887429-29445-1-git-send-email-weiyi.lu@mediatek.com>
Add clock controller nodes for SoC mt8192
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++++++++++++++++++++++++++++++
1 file changed, 163 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024..92dcfbd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -5,6 +5,7 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -213,6 +214,24 @@
};
};
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8192-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8192-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8192-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0 0x10005000 0 0x1000>,
@@ -238,6 +257,12 @@
#interrupt-cells = <2>;
};
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8192-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
@@ -247,6 +272,12 @@
clock-names = "clk13m";
};
+ scp_adsp: syscon@10720000 {
+ compatible = "mediatek,mt8192-scp_adsp", "syscon";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt8192-uart",
"mediatek,mt6577-uart";
@@ -267,6 +298,12 @@
status = "disabled";
};
+ imp_iic_wrap_c: syscon@11007000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_c", "syscon";
+ reg = <0 0x11007000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
spi0: spi@1100a000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
@@ -379,6 +416,12 @@
status = "disabled";
};
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c3: i2c3@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
@@ -392,6 +435,12 @@
status = "disabled";
};
+ imp_iic_wrap_e: syscon@11cb1000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_e", "syscon";
+ reg = <0 0x11cb1000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c7: i2c7@11d00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d00000 0 0x1000>,
@@ -431,6 +480,12 @@
status = "disabled";
};
+ imp_iic_wrap_s: syscon@11d03000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_s", "syscon";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c1: i2c1@11d20000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d20000 0 0x1000>,
@@ -470,6 +525,12 @@
status = "disabled";
};
+ imp_iic_wrap_ws: syscon@11d23000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_ws", "syscon";
+ reg = <0 0x11d23000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c5: i2c5@11e00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11e00000 0 0x1000>,
@@ -483,6 +544,12 @@
status = "disabled";
};
+ imp_iic_wrap_w: syscon@11e01000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_w", "syscon";
+ reg = <0 0x11e01000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c0: i2c0@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
@@ -508,5 +575,101 @@
#size-cells = <0>;
status = "disabled";
};
+
+ imp_iic_wrap_n: syscon@11f02000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_n", "syscon";
+ reg = <0 0x11f02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc_top: syscon@11f10000 {
+ compatible = "mediatek,mt8192-msdc_top", "syscon";
+ reg = <0 0x11f10000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc: syscon@11f60000 {
+ compatible = "mediatek,mt8192-msdc", "syscon";
+ reg = <0 0x11f60000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mfgcfg: syscon@13fbf000 {
+ compatible = "mediatek,mt8192-mfgcfg", "syscon";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8192-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: syscon@15020000 {
+ compatible = "mediatek,mt8192-imgsys", "syscon";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys2: syscon@15820000 {
+ compatible = "mediatek,mt8192-imgsys2", "syscon";
+ reg = <0 0x15820000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: syscon@1600f000 {
+ compatible = "mediatek,mt8192-vdecsys_soc", "syscon";
+ reg = <0 0x1600f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@1602f000 {
+ compatible = "mediatek,mt8192-vdecsys", "syscon";
+ reg = <0 0x1602f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@17000000 {
+ compatible = "mediatek,mt8192-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@1a000000 {
+ compatible = "mediatek,mt8192-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: syscon@1a04f000 {
+ compatible = "mediatek,mt8192-camsys_rawa", "syscon";
+ reg = <0 0x1a04f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: syscon@1a06f000 {
+ compatible = "mediatek,mt8192-camsys_rawb", "syscon";
+ reg = <0 0x1a06f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawc: syscon@1a08f000 {
+ compatible = "mediatek,mt8192-camsys_rawc", "syscon";
+ reg = <0 0x1a08f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: syscon@1b000000 {
+ compatible = "mediatek,mt8192-ipesys", "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mdpsys: syscon@1f000000 {
+ compatible = "mediatek,mt8192-mdpsys", "syscon";
+ reg = <0 0x1f000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
--
1.8.1.1.dirty
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next prev parent reply other threads:[~2020-11-09 2:15 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-09 2:03 [PATCH v5 00/24] Mediatek MT8192 clock support Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 01/24] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 02/24] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 03/24] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 04/24] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 05/24] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 06/24] clk: mediatek: Add dt-bindings of MT8192 clocks Weiyi Lu
2020-11-10 16:03 ` Rob Herring
2020-11-09 2:03 ` [PATCH v5 07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2020-11-18 3:55 ` Ikjoon Jang
2020-11-18 5:21 ` Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 08/24] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 09/24] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 10/24] clk: mediatek: Add MT8192 basic clocks support Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 11/24] clk: mediatek: Add MT8192 audio clock support Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 12/24] clk: mediatek: Add MT8192 camsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 13/24] clk: mediatek: Add MT8192 imgsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 14/24] clk: mediatek: Add MT8192 imp i2c wrapper " Weiyi Lu
2020-11-18 2:41 ` Yingjoe Chen
2020-11-18 3:49 ` Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 15/24] clk: mediatek: Add MT8192 ipesys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 16/24] clk: mediatek: Add MT8192 mdpsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 17/24] clk: mediatek: Add MT8192 mfgcfg " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 18/24] clk: mediatek: Add MT8192 mmsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 19/24] clk: mediatek: Add MT8192 msdc " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 20/24] clk: mediatek: Add MT8192 scp adsp " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 21/24] clk: mediatek: Add MT8192 vdecsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 22/24] clk: mediatek: Add MT8192 vencsys " Weiyi Lu
2020-11-09 2:03 ` Weiyi Lu [this message]
2020-11-23 4:02 ` [PATCH v5 23/24] arm64: dts: mediatek: Add mt8192 clock controllers Ikjoon Jang
2020-12-17 8:53 ` Stephen Boyd
2020-11-09 2:03 ` [PATCH v5 24/24] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Weiyi Lu
2020-12-17 9:19 ` [PATCH v5 00/24] Mediatek MT8192 clock support Stephen Boyd
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