From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: Weiyi Lu <weiyi.lu@mediatek.com>,
srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org,
Yingjoe Chen <yingjoe.chen@mediatek.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 24/24] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
Date: Mon, 9 Nov 2020 10:03:49 +0800 [thread overview]
Message-ID: <1604887429-29445-25-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1604887429-29445-1-git-send-email-weiyi.lu@mediatek.com>
infra_uart0 clock is the real one what uart0 uses as bus clock.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 92dcfbd..ac5dca6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -283,7 +283,7 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
--
1.8.1.1.dirty
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
next prev parent reply other threads:[~2020-11-09 2:16 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-09 2:03 [PATCH v5 00/24] Mediatek MT8192 clock support Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 01/24] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 02/24] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 03/24] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 04/24] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 05/24] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 06/24] clk: mediatek: Add dt-bindings of MT8192 clocks Weiyi Lu
2020-11-10 16:03 ` Rob Herring
2020-11-09 2:03 ` [PATCH v5 07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2020-11-18 3:55 ` Ikjoon Jang
2020-11-18 5:21 ` Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 08/24] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 09/24] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 10/24] clk: mediatek: Add MT8192 basic clocks support Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 11/24] clk: mediatek: Add MT8192 audio clock support Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 12/24] clk: mediatek: Add MT8192 camsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 13/24] clk: mediatek: Add MT8192 imgsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 14/24] clk: mediatek: Add MT8192 imp i2c wrapper " Weiyi Lu
2020-11-18 2:41 ` Yingjoe Chen
2020-11-18 3:49 ` Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 15/24] clk: mediatek: Add MT8192 ipesys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 16/24] clk: mediatek: Add MT8192 mdpsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 17/24] clk: mediatek: Add MT8192 mfgcfg " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 18/24] clk: mediatek: Add MT8192 mmsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 19/24] clk: mediatek: Add MT8192 msdc " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 20/24] clk: mediatek: Add MT8192 scp adsp " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 21/24] clk: mediatek: Add MT8192 vdecsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 22/24] clk: mediatek: Add MT8192 vencsys " Weiyi Lu
2020-11-09 2:03 ` [PATCH v5 23/24] arm64: dts: mediatek: Add mt8192 clock controllers Weiyi Lu
2020-11-23 4:02 ` Ikjoon Jang
2020-12-17 8:53 ` Stephen Boyd
2020-11-09 2:03 ` Weiyi Lu [this message]
2020-12-17 9:19 ` [PATCH v5 00/24] Mediatek MT8192 clock support Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1604887429-29445-25-git-send-email-weiyi.lu@mediatek.com \
--to=weiyi.lu@mediatek.com \
--cc=drinkcat@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=srv_heupstream@mediatek.com \
--cc=yingjoe.chen@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox