Re: [PATCH 3/4] mmc: mediatek: Add tune support

[Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>]

On Thu, Oct 15, 2015 at 04:40:02PM +0800, Chaotian Jing wrote:
> On Thu, 2015-10-15 at 08:29 +0200, Sascha Hauer wrote:
> > Hi,
> > 
> > On Tue, Oct 13, 2015 at 05:37:57PM +0800, Chaotian Jing wrote:
> > > @@ -1260,6 +1547,16 @@ static int msdc_drv_probe(struct platform_device *pdev)
> > >  		goto host_free;
> > >  	}
> > >  
> > > +	host->src_clk_parent = clk_get_parent(host->src_clk);
> > > +	host->hs400_src = devm_clk_get(&pdev->dev, "400mhz");
> > > +	if (IS_ERR(host->hs400_src)) {
> > > +		dev_dbg(&pdev->dev, "Cannot find 400mhz at dts!\n");
> > > +	} else if (clk_set_parent(host->src_clk_parent, host->hs400_src) < 0) {
> > > +		dev_err(host->dev, "Failed to set 400mhz source clock!\n");
> > > +		ret = -EINVAL;
> > > +		goto host_free;
> > > +	}
> > 
> > This is a static setup. We have device tree bindings for doing this.
> > Please look for assigned-clocks and assigned-clock-parents. Doing stuff
> > like this in the driver almost certainly leads to problems because the
> > next SoC will have different requirements here.
> > 
> 
> Sorry, I cannot understand it, could you help to give some sample code
> about this ?

	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>
	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>

Have a look at drivers/clk/clk-conf.c and
Documentation/devicetree/bindings/clock/clock-bindings.txt

Sascha

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