From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: Anan Sun <anan.sun@mediatek.com>,
devicetree@vger.kernel.org, Jun Yan <jun.yan@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
Chao Hao <chao.hao@mediatek.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org,
Yong Wu <yong.wu@mediatek.com>,
Cui Zhang <zhang.cui@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 11/19] iommu/mediatek: Remove pgtable info in mtk_iommu_domain
Date: Sun, 5 Jan 2020 18:45:15 +0800 [thread overview]
Message-ID: <20200105104523.31006-12-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com>
This patch will use mtk_iommu_pgtable to replace the part
of pgtable in mtk_iommu_domain, so we can remove the information
of pgtable in mtk_iommu_domain.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 37 +++++++++++++++++--------------------
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index cfefdd638f1a..b34bd3abccf8 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -111,9 +111,6 @@
#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
struct mtk_iommu_domain {
- struct io_pgtable_cfg cfg;
- struct io_pgtable_ops *iop;
-
struct iommu_domain domain;
};
@@ -373,6 +370,10 @@ static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data,
/* binding to pgtable */
data->pgtable = pgtable;
+ /* update HW settings */
+ writel(pgtable->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
+ data->base + REG_MMU_PT_BASE_ADDR);
+
dev_info(data->dev, "m4u%d attach_pgtable done!\n", data->m4u_id);
return 0;
@@ -398,8 +399,6 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (iommu_get_dma_cookie(&dom->domain))
goto free_dom;
- dom->cfg = pgtable->cfg;
- dom->iop = pgtable->iop;
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap;
@@ -416,11 +415,12 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
static void mtk_iommu_domain_free(struct iommu_domain *domain)
{
- struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
- free_io_pgtable_ops(dom->iop);
iommu_put_dma_cookie(domain);
kfree(to_mtk_domain(domain));
+ free_io_pgtable_ops(pgtable->iop);
+ kfree(pgtable);
}
static int mtk_iommu_attach_device(struct iommu_domain *domain,
@@ -433,11 +433,8 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
return -ENODEV;
/* Update the pgtable base address register of the M4U HW */
- if (!data->m4u_dom) {
+ if (!data->m4u_dom)
data->m4u_dom = dom;
- writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
- data->base + REG_MMU_PT_BASE_ADDR);
- }
mtk_iommu_config(data, dev, true);
return 0;
@@ -457,7 +454,7 @@ static void mtk_iommu_detach_device(struct iommu_domain *domain,
static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
{
- struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
/* The "4GB mode" M4U physically can not use the lower remap of Dram. */
@@ -465,16 +462,16 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
paddr |= BIT_ULL(32);
/* Synchronize with the tlb_lock */
- return dom->iop->map(dom->iop, iova, paddr, size, prot);
+ return pgtable->iop->map(pgtable->iop, iova, paddr, size, prot);
}
static size_t mtk_iommu_unmap(struct iommu_domain *domain,
unsigned long iova, size_t size,
struct iommu_iotlb_gather *gather)
{
- struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
- return dom->iop->unmap(dom->iop, iova, size, gather);
+ return pgtable->iop->unmap(pgtable->iop, iova, size, gather);
}
static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
@@ -498,11 +495,11 @@ static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
dma_addr_t iova)
{
- struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
phys_addr_t pa;
- pa = dom->iop->iova_to_phys(dom->iop, iova);
+ pa = pgtable->iop->iova_to_phys(pgtable->iop, iova);
if (data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
pa &= ~BIT_ULL(32);
@@ -845,8 +842,8 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
static int __maybe_unused mtk_iommu_resume(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
+ struct mtk_iommu_pgtable *pgtable = data->pgtable;
struct mtk_iommu_suspend_reg *reg = &data->reg;
- struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
void __iomem *base = data->base;
int ret;
@@ -864,8 +861,8 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
- if (m4u_dom)
- writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
+ if (pgtable)
+ writel(pgtable->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
base + REG_MMU_PT_BASE_ADDR);
return 0;
}
--
2.18.0
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next prev parent reply other threads:[~2020-01-05 11:00 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
2020-01-05 10:45 ` [PATCH v2 01/19] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-01-06 21:57 ` Rob Herring
2020-01-07 11:10 ` chao hao
2020-01-05 10:45 ` [PATCH v2 02/19] iommu/mediatek: Add m4u1_mask to distinguish m4u_id Chao Hao
2020-01-05 10:45 ` [PATCH v2 03/19] iommu/mediatek: Extend larb_remap to larb_remap[2] Chao Hao
2020-01-05 10:45 ` [PATCH v2 04/19] iommu/mediatek: Rename offset=0x48 register Chao Hao
2020-01-05 10:45 ` [PATCH v2 05/19] iommu/mediatek: Put inv_sel_reg in the plat_data for preparing add 0x2c support in mt6779 Chao Hao
2020-01-05 10:45 ` [PATCH v2 06/19] iommu/mediatek: Add new flow to get SUB_COMMON ID in translation fault Chao Hao
2020-01-05 10:45 ` [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779 Chao Hao
2020-01-05 10:45 ` [PATCH v2 08/19] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-01-05 10:45 ` [PATCH v2 09/19] iommu/mediatek: Add mtk_iommu_pgtable structure Chao Hao
2020-01-05 10:45 ` [PATCH v2 10/19] iommu/mediatek: Remove mtk_iommu_domain_finalise Chao Hao
2020-01-05 10:45 ` Chao Hao [this message]
2020-01-05 10:45 ` [PATCH v2 12/19] iommu/mediatek: Change get the way of m4u_group Chao Hao
2020-01-05 10:45 ` [PATCH v2 13/19] iommu/mediatek: Add smi_larb info about device Chao Hao
2020-01-05 10:45 ` [PATCH v2 14/19] iommu/mediatek: Add mtk_domain_data structure Chao Hao
2020-01-05 10:45 ` [PATCH v2 15/19] iommu/mediatek: Remove the usage of m4u_dom variable Chao Hao
2020-01-05 10:45 ` [PATCH v2 16/19] iommu/mediatek: Remove mtk_iommu_get_m4u_data api Chao Hao
2020-01-05 10:45 ` [PATCH v2 17/19] iommu/mediatek: Add iova reserved function Chao Hao
2020-01-05 10:45 ` [PATCH v2 18/19] iommu/mediatek: Change single domain to multiple domains Chao Hao
2020-01-05 10:45 ` [PATCH v2 19/19] iommu/mediatek: Add multiple mtk_iommu_domain support for mt6779 Chao Hao
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